C5517 clock out jitter

Are you referring to the CLKOUT pin of the device? Device CLKOUT is specifiy for debug purpose only. Also, please provide associated device pin names to graphs.
Regards.

You can probably clean it up by changing the PLL settings.

Let us know which clock pin you are measuring.

Also let us know your PLL and pin configurations (clock frequency and register values) from input to pre divider clock to post divider(s) to clockout sel.

Hope this helps,
Mark

Yes, I measured CLKOUT pin and compared with CLKIN.

The input clk is 16.384MHz to C5517 and the PLL settings lists below.
MOV #0101111100000000b, port(#PMR) ; PLL mult = (0x5F00 / 256) + 1 = 96
MOV #0000000000000011b, port(#PICR) ; PLL reference divider = 4, 16.384MHz / 4 = 4.096Mhz Ref freq
MOV #0000000000000000b, port(#PODCR); Output divider = 0 (OD = 0 + 1 = 1, OD2 = (0 + 1) * 2 = 2, OUTDIV2BY = 0)
MOV #0000000000000000b, port(#PCR) ; Normal operating mode
After that, I generated the 8.192MHz from McBSP_CLKX and found the phase noise was bad.
So, I measured C5517 General Purpose EVM's CLKOUT on HEADER3 to check it hardware or software issue.
http://support.spectrumdigital.com/boards/evm5517/revf/

I didn't happen this issue before when using 5409,5506 and 5507.
It looks like internal PLL design was modified on 5515 and 5517.

Hi All

I have some problem.

I use C5517-EVM with McBSP_Master_AIC3204_48kbps_POLL

I captured the waveform of McBSP_CLKX (L10) as below.

How can I improve the clock jitter?      

From:

TMDSEVM5517 :

TMS320VC55XCSL-LOWPWR  03_04_00_02 :

C:\c55_lp\c55_csl_3.04\c55xx_csl\ccs_v5.0_examples\mcbsp\McBSP_Master_AIC3204_48kbps_POLL

By Will