C5535 togle from 32 KHz Quartz to 12 MHzClKin

As described in Power Configurations table in TRM, RTC clock must be running for RTC only mode. It can be turned off only when it is not used. In RTC only mode, it is used.
Regards.

Hi Steve,

I know about this.
My setup is the following :
* in RTC Only mode, C5535 is running using its 32.768 KHz crystal : OK
* in active mode, C5535 must be running from its CLKIn with a 12 MHz oscillator.

In order to reduce power consumption, in RTC only mode, I would like the DSP to put the external 12 MHz oscillator to be in sleep mode.
Switching from RTC only mode to active mode with the Wake up pin, DSP should power on the 12 MHz oscillator before, but It can't since it is in RTC only mode.
As a conclusion, trying to keep power consumption putting the external 12 MHz oscillator in sleep mode, the DSP will never be able to wake-up.
I have double checked : CLK_sel pin is not allowed to change during device operation; it must be tied high or low at the board.

Any idea please ?
Thanks.

Nicolas

Well, I think of this as similiar to the "chicken and egg" thing. Thus we have to have certain assumption which is clocked by the 32k RTC osc. It is low power and can be used to generate the higher operational clock frequency for the device via PLL. When going to RTC only mode, we shut off the PLL and all possible power to achieve a low power state. When waken up, the device activates DSP_LDO to bring up the system.
Regards.

Hi,

The issue is that I use the DSP with a codec (AIC3204), and I have to be sure that both are using the same ref clk. Note that Codec is in Master mode.
If the DSP use the 32.768 crystal and the codec the 12 MHz oscillator, I know that my I²S data between DSP and Codec will be fine, but my other software framework won't work.
As a conclusion, the DSP must use the 12 MHz ref clk, not the 32.768 KHz crystal. But I also need to switch off the oscillator when the DSP in RTC Only mode ...
So yes, this is a kind of Chicken/egg/race condition.

Any idea ?
Note that BCLK=8 Ksps and BCLK=2x8x16=256 KHz.

Thanks.

Nicolas

Steve,

One other thing : it is mandatory that the DSP PLL run at 98.304 MHz.
As far as I remember, DSP can't be in MAster I²S at 8Ksps with such 98.304 MHz.

Nicolas

Steve,

Some other information regarding DSP PLL configuration:

// Use the 32.768 kHz internal clock
PLL_Config pllCfg_98MHz = {0x8BB4, 0x8000, 0x0806, 0x0000}; /* Ratio 2996 + 4 */

// Use the 12 MHz reference clock
// Nominal Frequency = 98.304 MHz = (12.0 MHz/125) * 1024
// Multiplier M = 1020 + 4
// Reference divider N = 121 + 4
PLL_Config pllCfg_98MHz = {0x83FC, 0x0079, 0x0806, 0x0000};

So I wonder if using the 32.768 KHz crystal, I can have both the PLL at 98.304 MHz and I²S at 8Ksps with BCLK at 256 KHz (16 bits legnth). I can perhaps check if I²S BCLK to be 16, 20, 24 or 32 bits to fit this condition. In that hypothesis, WCLK is still 8Ksps, but BCLK is
16 word length: 256 KHz
20 word length: 320 KHz
24 word length: 384 KHz
32 word length: 512 KHz

If you find a clock configuration for both DSP (98.304 MHz) and Codec (8Ksps) from 32.768 Crystal, so I will be able to remove 12 MHz ref clock.

Thanks

Nicolas

No. PLLOUT is only spec'ed for max 100MHz with CVDD = 1.3V and 60MHz at CVDD = 1.05V ( Table 6-3 in data manual).
Regards.

Steve,

I have found in datasheet that with 92.304 MHz sys clcok, it is impossible to have a 8KHz WCLK (WCLK=SYSCLK/2^(DIV+1)).
I will check if I can drive the codec from a 32.768 Khz freq and rather use Codec PLL to generate 8KHz from 32.768 KHz (multiplier is 4096)

Nicolas