C5515 timer and DMA issue

Nitin Chavan1

Hi,

I am combining code for DMA in pingpong mode and timer in autoreload mode. I have observed the timer interrupt is not working. Please help me to sort this issue.

please find the below settings for timer initialization and ISR. I have also pasted the DMA initialization and ISR.

2388.timer.c

/**********************************************************************
**+-----------------------------------------------------------------+**
**|                            ****                                 |**
**|                            ****                                 |**
**|                            ******o***                           |**
**|                      ********_///_****                          |**
**|                      ***** /_//_/ ****                          |**
**|                       ** ** (__/ ****                           |**
**|                           *********                             |**
**|                            ****                                 |**
**|                            ***                                  |**
**|                                                                 |**
**|   Copyright (c) 2006 - 2010    Texas Instruments Incorporated   |**
**|                        ALL RIGHTS RESERVED                      |**
**|                                                                 |**
**| Permission is hereby granted to licensees of Texas Instruments  |**
**| Incorporated (TI) products to use this computer program for     |**
**| the sole purpose of implementing a licensee product based       |**
**| on TI products.No other rights to reproduce, use, or            |**
**| disseminate this computer program, whether in part or in whole, |**
**| are granted.TI makes no representation or warranties with       |**
**| respect to the performance of this computer program, and        |**
**| specifically disclaims any responsibility for any damages,      |**
**| special or consequential,connected with the use of this program.|**
**|                                                                 |**
**+-----------------------------------------------------------------+**
**********************************************************************/
#include "data_types.h"
#include "timer.h"
#include "register_cpu.h"


void Timer0Init(void)
{

	/*  Timer0 Initialization */
// timer interval 10msec
// prescale = 0 (devide by 2)
// 100/2 = 50MHz ==> 20 nsec
// 10msec/20nsec = 500000 (0x7A120)

	/* TIM0 EN | AutoReload disable | Prescale = 0(100/2 = 50MHz) ==> 20nsec */
	*CPU_TIM0_CTRL = 0x8002; 	// autoReload
//    *CPU_TIM0_CTRL = 0x8000; 	// disable autoReload

	*CPU_TIM0_PLWR = 0xA120;
	*CPU_TIM0_PHWR = 0x0007; 

	*CPU_TIM0_CLWR = 0x0000;
	*CPU_TIM0_CHWR = 0x0000;
	
	/*  Clearing timer Aggregation register*/
	*CPU_TIMINT_AGGR = 0x0007;

	/*  enable timer0 int flag*/
	*CPU_TIM0_IER = 0x0001;
}

void StartTimer0(void)
{
	/* Start the Timer 0*/
	*CPU_TIM0_CTRL = *CPU_TIM0_CTRL | 0x0001; 
}


interrupt void Timer_isr(void)
{

    // clear timer int flag
    IFR0 = IFR0&0x0010; 
    
	/*  clear timer0 int flag*/
	*CPU_TIM0_IER = 0x0001;
	    
	/*	Clear Timer0 bit in Timer Aggregate register*/
	*CPU_TIMINT_AGGR = *CPU_TIMINT_AGGR | 0x0001 ;	

    //StartTimer0();
}

dma.c

/******************************************************************************
**+-------------------------------------------------------------------------+**
**|                            ****                                         |**
**|                            ****                                         |**
**|                            ******o***                                   |**
**|                      ********_///_****                                  |**
**|                      ***** /_//_/ ****                                  |**
**|                       ** ** (__/ ****                                   |**
**|                           *********                                     |**
**|                            ****                                         |**
**|                            ***                                          |**
**|                                                                         |**
**|         Copyright (c) 2006 - 2010    Texas Instruments Incorporated     |**
**|                        ALL RIGHTS RESERVED                              |**
**|                                                                         |**
**| Permission is hereby granted to licensees of Texas Instruments          |**
**| Incorporated (TI) products to use this computer program for the sole    |**
**| purpose of implementing a licensee product based on TI products.        |**
**| No other rights to reproduce, use, or disseminate this computer         |**
**| program, whether in part or in whole, are granted.                      |**
**|                                                                         |**
**| TI makes no representation or warranties with respect to the            |**
**| performance of this computer program, and specifically disclaims        |**
**| any responsibility for any damages, special or consequential,           |**
**| connected with the use of this program.                                 |**
**|                                                                         |**
**+-------------------------------------------------------------------------+**
******************************************************************************/
#include "data_types.h"
#include "register_dma.h"
#include "register_cpu.h"
#include "dma.h"
#include "i2s.h"

#define XMIT_BUFF_SIZE  48
#define AUTO_RELOAD     1
#define SINE_WAVE       2

Int16 RcvL1[XMIT_BUFF_SIZE];
Int16 RcvR1[XMIT_BUFF_SIZE];
Int16 RcvL2[XMIT_BUFF_SIZE];
Int16 RcvR2[XMIT_BUFF_SIZE];

Uint32 RxL1_DMA_address;
Uint32 RxL2_DMA_address;
Uint32 RxR1_DMA_address;
Uint32 RxR2_DMA_address;
Uint32 TxL1_DMA_address;
Uint32 TxL2_DMA_address;
Uint32 TxR1_DMA_address;
Uint32 TxR2_DMA_address;

Uint16 CurrentRxL_DMAChannel =1;
Uint16 CurrentRxR_DMAChannel =1;

Uint16 CurrentTxL_DMAChannel =1;
Uint16 CurrentTxR_DMAChannel =1;
// 1: L1, R1 channel
// 2: L2, R2 channel 

// -3dB 1 KHz sine sampled at 48 KHz
Int16 XmitL_Sine_1K[XMIT_BUFF_SIZE] = {
0x0000,0x0B6C,0x16A6,0x217C,0x2BC0,0x3544,0x3DDF,0x456B, 
0x4BC7,0x50D7,0x5485,0x56C0,0x5780,0x56C0,0x5485,0x50D7, 
0x4BC7,0x456B,0x3DDF,0x3544,0x2BC0,0x217C,0x16A6,0x0B6C, 
0x0000,0xF494,0xE95A,0xDE84,0xD440,0xCABC,0xC221,0xBA95, 
0xB439,0xAF29,0xAB7B,0xA940,0xA880,0xA940,0xAB7B,0xAF29, 
0xB439,0xBA95,0xC221,0xCABC,0xD440,0xDE84,0xE95A,0xF494
};

//-3 dB 2 KHz sine sampled at 48 KHz
Int16 XmitL_Sine_2K[XMIT_BUFF_SIZE] = {
0x0000,0x16A6,0x2BC0,0x3DDF,0x4BC7,0x5485,0x5780,0x5485, 
0x4BC7,0x3DDF,0x2BC0,0x16A6,0x0000,0xE95A,0xD440,0xC221, 
0xB439,0xAB7B,0xA880,0xAB7B,0xB439,0xC221,0xD440,0xE95A,
0x0000,0x16A6,0x2BC0,0x3DDF,0x4BC7,0x5485,0x5780,0x5485, 
0x4BC7,0x3DDF,0x2BC0,0x16A6,0x0000,0xE95A,0xD440,0xC221, 
0xB439,0xAB7B,0xA880,0xAB7B,0xB439,0xC221,0xD440,0xE95A
};

// -3dB 1 KHz sine sampled at 48 KHz
Int16 XmitR_Sine_1K[XMIT_BUFF_SIZE] = {
0x0000,0x0B6C,0x16A6,0x217C,0x2BC0,0x3544,0x3DDF,0x456B, 
0x4BC7,0x50D7,0x5485,0x56C0,0x5780,0x56C0,0x5485,0x50D7, 
0x4BC7,0x456B,0x3DDF,0x3544,0x2BC0,0x217C,0x16A6,0x0B6C, 
0x0000,0xF494,0xE95A,0xDE84,0xD440,0xCABC,0xC221,0xBA95, 
0xB439,0xAF29,0xAB7B,0xA940,0xA880,0xA940,0xAB7B,0xAF29, 
0xB439,0xBA95,0xC221,0xCABC,0xD440,0xDE84,0xE95A,0xF494
};

//-3 dB 2 KHz sine sampled at 48 KHz
Int16 XmitR_Sine_2K[XMIT_BUFF_SIZE] = {
0x0000,0x16A6,0x2BC0,0x3DDF,0x4BC7,0x5485,0x5780,0x5485, 
0x4BC7,0x3DDF,0x2BC0,0x16A6,0x0000,0xE95A,0xD440,0xC221, 
0xB439,0xAB7B,0xA880,0xAB7B,0xB439,0xC221,0xD440,0xE95A,
0x0000,0x16A6,0x2BC0,0x3DDF,0x4BC7,0x5485,0x5780,0x5485, 
0x4BC7,0x3DDF,0x2BC0,0x16A6,0x0000,0xE95A,0xD440,0xC221, 
0xB439,0xAB7B,0xA880,0xAB7B,0xB439,0xC221,0xD440,0xE95A
};

//Int16 XmitL_Sine_1K[XMIT_BUFF_SIZE]={0};
//Int16 XmitL_Sine_2K[XMIT_BUFF_SIZE]={0};
//Int16 XmitR_Sine_1K[XMIT_BUFF_SIZE]={0};
//Int16 XmitR_Sine_2K[XMIT_BUFF_SIZE]={0};

Int16 RcvL_Sine[XMIT_BUFF_SIZE]={0};
Int16 RcvR_Sine[XMIT_BUFF_SIZE]={0};
Uint16 DMA_Count =0, Error_Count_L =0, Error_Count_R =0;
Uint16 DMA_Done = 0;
extern Uint16 fSineWave;
void setDMA_address(void)
{

    // just bypass with double buffering, for checking ping-pong buffer 
    RxL1_DMA_address = (Uint32)RcvL1;   
    RxL1_DMA_address = (RxL1_DMA_address<<1) + 0x10000;		// change word address to byte address and add DARAM offset for DMA

    RxL2_DMA_address = (Uint32)RcvL2;   
    RxL2_DMA_address = (RxL2_DMA_address<<1) + 0x10000;		// change word address to byte address and add DARAM offset for DMA

    RxR1_DMA_address = (Uint32)RcvR1;   
    RxR1_DMA_address = (RxR1_DMA_address<<1) + 0x10000;		// change word address to byte address and add DARAM offset for DMA

    RxR2_DMA_address = (Uint32)RcvR2;   
    RxR2_DMA_address = (RxR2_DMA_address<<1) + 0x10000;		// change word address to byte address and add DARAM offset for DMA

    TxL1_DMA_address = (Uint32)RcvL2;   
    TxL1_DMA_address = (TxL1_DMA_address<<1) + 0x10000;		// change word address to byte address and add DARAM offset for DMA

    TxL2_DMA_address = (Uint32)RcvL1;   
    TxL2_DMA_address = (TxL2_DMA_address<<1) + 0x10000;		// change word address to byte address and add DARAM offset for DMA
    
    TxR1_DMA_address = (Uint32)RcvR2;   
    TxR1_DMA_address = (TxR1_DMA_address<<1) + 0x10000;		// change word address to byte address and add DARAM offset for DMA
    
    TxR2_DMA_address = (Uint32)RcvR1;   
    TxR2_DMA_address = (TxR2_DMA_address<<1) + 0x10000;		// change word address to byte address and add DARAM offset for DMA      


    
}

void set_dma1_ch0_stop(void)
{
	Uint16 temp;
//  DMA stop
    temp = DMA1_CH0_TC_MSW;
	temp &= 0x7FFF;
	DMA1_CH0_TC_MSW = temp;    
}

void set_dma1_ch1_stop(void)
{
	Uint16 temp;
//  DMA stop
    temp = DMA1_CH1_TC_MSW;
	temp &= 0x7FFF;
	DMA1_CH1_TC_MSW = temp;    
}

Uint16 set_dma1_ch0_i2s2_Lout(void)
{
	Uint16 temp; 
	Uint32 add;

    DMA1_CH0_TC_LSW = XMIT_BUFF_SIZE*2;
 
#if(AUTO_RELOAD ==1)        
    DMA1_CH0_TC_MSW = 0x3204;     //src incre, destination fix, sync, auto  
#else
    DMA1_CH0_TC_MSW = 0x2204;     //src incre, destination fix, sync, No auto  
#endif
                
	temp = DMA1_CH10_EVENT_SRC;
    DMA1_CH10_EVENT_SRC = temp | 0x0001;   // I2S2 transmit event
    
//    if(fSineWave ==1)
//    {
//        add = (Uint32)XmitL_Sine_1K;        
//    }
//    else
//    {
//        add = (Uint32)XmitL_Sine_2K;        
//    }
//     add = (Uint32)XmitL_Sine_1K;    
//    add = (add<<1) + 0x10000;		// change word address to byte address and add DARAM offset for DMA
    DMA1_CH0_SRC_LSW = (Uint16)TxL1_DMA_address;
    
    DMA1_CH0_SRC_MSW = 0xFFFF & (TxL1_DMA_address >> 16);
    
    DMA1_CH0_DST_LSW = 0x2A08;      // is20 transmit left data register lsw
    
//  DMA starts   
    temp = DMA1_CH0_TC_MSW;
	temp |= 0x8000;
	DMA1_CH0_TC_MSW = temp;

    return SUCCESS;
}

Uint16 set_dma1_ch1_i2s2_Rout(void)
{	
	Uint16 temp;
	Uint32 add;

    DMA1_CH1_TC_LSW = XMIT_BUFF_SIZE*2;
//    DMA0_CH1_TC_LSW = 8;

#if(AUTO_RELOAD ==1)            
    DMA1_CH1_TC_MSW = 0x3204;     //src incre, destination fix, sync, auto
#else    
    DMA1_CH1_TC_MSW = 0x2204;     //src incre, destination fix, sync, No auto
#endif
            
	temp = DMA1_CH10_EVENT_SRC;
    DMA1_CH10_EVENT_SRC = temp | 0x0100;   // I2S2 transmit event
    
//    if(fSineWave ==1)
//    {
//        add = (Uint32)XmitR_Sine_1K;        
//    }
//    else
//    {
//        add = (Uint32)XmitR_Sine_2K;        
//    }  
//    add = (Uint32)XmitR_Sine_1K;          
//    add = (add<<1) + 0x10000;		//// change word address to byte address and add DARAM offset for DMA
    DMA1_CH1_SRC_LSW = (Uint16)TxR1_DMA_address;
    
    DMA1_CH1_SRC_MSW = 0xFFFF & (TxR1_DMA_address >> 16);
    
    DMA1_CH1_DST_LSW = 0x2A0C;      // is20 transmit right data register lsw

// DMA starts    
    temp = DMA1_CH1_TC_MSW;
	temp |= 0x8000;
	DMA1_CH1_TC_MSW = temp;


    return SUCCESS;
}

Uint16 set_dma1_ch2_i2s2_Lin(void)
{
	Uint16 temp; 
	Uint32 add;
	
    DMA1_CH2_TC_LSW = XMIT_BUFF_SIZE*2;

#if(AUTO_RELOAD ==1)        
    DMA1_CH2_TC_MSW = 0x3084;     //src fix, destination increase, sync, auto, int 
#else
    DMA1_CH2_TC_MSW = 0x2084;     //src fix, destination increase,, No auto, int
#endif
                
	temp = DMA1_CH32_EVENT_SRC;
    DMA1_CH32_EVENT_SRC = temp | 0x0002;   // I2S2 receive event
    
//    add=(Uint16)RcvL_Sine;
//  	add = (add<<1) + 0x10000;		//// change word address to byte address and add DARAM offset for DMA
    DMA1_CH2_DST_LSW = RxL1_DMA_address;  
    DMA1_CH2_DST_MSW = 0xFFFF & (RxL1_DMA_address >> 16);
    
    DMA1_CH2_SRC_LSW = 0x2A28;      // is22 receive left data register lsw
    DMA1_CH2_SRC_MSW = 0;

//    CurrentRxL_DMAChannel =1;
//  DMA starts   
    temp = DMA1_CH2_TC_MSW;
	temp |= 0x8000;
	DMA1_CH2_TC_MSW = temp;

    return SUCCESS;
}

Uint16 set_dma1_ch3_i2s2_Rin(void)
{
	Uint16 temp; 
	Uint32 add;

    DMA1_CH3_TC_LSW = XMIT_BUFF_SIZE*2;

#if(AUTO_RELOAD ==1)        
    DMA1_CH3_TC_MSW = 0x3084;     //src fix, destination increase, sync, auto , int
#else
    DMA1_CH3_TC_MSW = 0x2084;     //src fix, destination increase,, No auto, int  
#endif
                
	temp = DMA1_CH32_EVENT_SRC;
    DMA1_CH32_EVENT_SRC = temp | 0x0200;   // I2S2 receive event
    
//    add=(Uint16)RcvR_Sine;
//  	add = (add<<1) + 0x10000;
    DMA1_CH3_DST_LSW = (Uint16)RxR1_DMA_address;
    DMA1_CH3_DST_MSW = 0xFFFF & (RxR1_DMA_address >> 16);
    
    DMA1_CH3_SRC_LSW = 0x2A2C;      // is22 receive right data register lsw
    DMA1_CH3_SRC_MSW = 0;

//    CurrentRxR_DMAChannel =1;
//  DMA starts   
    temp = DMA1_CH3_TC_MSW;
	temp |= 0x8000;
	DMA1_CH3_TC_MSW = temp;

    return SUCCESS;
}


void enable_dma_int(void)
{
    DMA_MSK = 0x00F0;     // enable all interrupts
    DMA_IFR = 0xFFFF;     // clear interrupt flags
}

//#if 1
//interrupt void DMA_Isr(void)
//{   
//    Uint16 temp,i;
//    	Uint32 add;
//    temp = IFR0;
//    IFR0 = temp;  
//
//	temp = DMA_IFR;
//    DMA_IFR = temp;     // clear interrupt flags
//
////#if(AUTO_RELOAD ==0) 
////    if(temp&0xF000 != 0)   // ch 2 of DMA3
////    {
////        for(i=0; i < XMIT_BUFF_SIZE; i++)
////        {
////            if (XmitL_Sine[i] != RcvL_Sine[i])
////            {
////    	        Error_Count_L++;
////    	        break;
////            }
////		}
////        for(i=0; i < XMIT_BUFF_SIZE; i++)
////        {
////       		if (XmitR_Sine[i] != RcvR_Sine[i])
////        	{
////    	    	Error_Count_R++;
////    		    break;
////    	    }
////	    }//for(temp=0; temp < XMIT_BUFF_SIZE; temp++)
////        DMA_Done = 1;
////    }
////#endif    	    
//  
//}
//#endif

interrupt void DMA_Isr(void)
{   
    Uint16 temp;//, dma_start;
    Uint32 add;
    temp = IFR0;
    IFR0 = temp&0x0100;  

	temp = DMA_IFR;
//    DMA_IFR = temp;     // clear interrupt flags

    if(temp&0x0010)
    {
//        // DMA TxL interrupt (channel 0)
        if(CurrentTxL_DMAChannel ==1)
        {
            CurrentTxL_DMAChannel =2;
            DMA1_CH0_SRC_LSW = (Uint16)TxL2_DMA_address;
            DMA1_CH0_SRC_MSW = 0xFFFF & (TxL2_DMA_address >> 16);
        
                
        }
        else
        {
            CurrentTxL_DMAChannel =1;
            DMA1_CH0_SRC_LSW = (Uint16)TxL1_DMA_address;
            DMA1_CH0_SRC_MSW = 0xFFFF & (TxL1_DMA_address >> 16);
        }
//    add = (Uint32)XmitL_Sine_1K;    
//    add = (add<<1) + 0x10000;		// change word address to byte address and add DARAM offset for DMA
//    DMA1_CH0_SRC_LSW = (Uint16)add;
        DMA_IFR = 0x0010;     // clear interrupt flags
//        temp = DMA1_CH0_TC_MSW;
//	    temp |= 0x8000;
//	    DMA1_CH0_TC_MSW = temp;
    } 
    else if(temp&0x0020)
    {
        // DMA TxR interrupt (channel 1)
        if(CurrentTxR_DMAChannel ==1)
        {
            CurrentTxR_DMAChannel =2;
            DMA1_CH1_SRC_LSW = (Uint16)TxR2_DMA_address;
            DMA1_CH1_SRC_MSW = 0xFFFF & (TxR2_DMA_address >> 16);
        }
        else
        {
            CurrentTxR_DMAChannel =1;
            DMA1_CH1_SRC_LSW = (Uint16)TxR1_DMA_address;
            DMA1_CH1_SRC_MSW = 0xFFFF & (TxR1_DMA_address >> 16);
        }
//   add = (Uint32)XmitR_Sine_1K;          
//    add = (add<<1) + 0x10000;		//// change word address to byte address and add DARAM offset for DMA
//    DMA1_CH1_SRC_LSW = (Uint16)add;
        DMA_IFR = 0x0020;     // clear interrupt flags        
//        temp = DMA1_CH1_TC_MSW;
//	    temp |= 0x8000;
//	    DMA1_CH1_TC_MSW = temp;    
//	    temp=I2S2_W0_MSW_R;    
    }
    else if(temp&0x0040)
    {
//        RunFilterForL =1;        
//        // DMA RxL interrupt (channel 2)
        if(CurrentRxL_DMAChannel ==1)
        {
            // change DMA Tx SRC address
            CurrentRxL_DMAChannel =2;

            DMA1_CH2_DST_LSW = (Uint16)RxL2_DMA_address;
            DMA1_CH2_DST_MSW = 0xFFFF & (RxL2_DMA_address >> 16);
        }
        else
        {
            CurrentRxL_DMAChannel =1;

            DMA1_CH2_DST_LSW = (Uint16)RxL1_DMA_address;
            DMA1_CH2_DST_MSW = 0xFFFF & (RxL1_DMA_address >> 16);
        }
////    add=(Uint16)RcvL_Sine;
////  	add = (add<<1) + 0x10000;		//// change word address to byte address and add DARAM offset for DMA
//    DMA1_CH2_DST_LSW = add;  
//    DMA1_CH2_DST_MSW = 0xFFFF & (add >> 16);
        DMA_IFR = 0x0040;     // clear interrupt flags        
//        temp = DMA1_CH2_TC_MSW;
//	    temp |= 0x8000;
//	    DMA1_CH2_TC_MSW = temp;        
    }
    else if(temp&0x0080)
    {
//        RunFilterForR =1;                
//        // DMA RxR interrupt (channel 3)
        if(CurrentRxR_DMAChannel ==1)
        {
            // change DMA Tx SRC address
            CurrentRxR_DMAChannel =2;

            DMA1_CH3_DST_LSW = (Uint16)RxR2_DMA_address;
            DMA1_CH3_DST_MSW = 0xFFFF & (RxR2_DMA_address >> 16);
        }
        else
        {
            CurrentRxR_DMAChannel =1;

            DMA1_CH3_DST_LSW = (Uint16)RxR1_DMA_address;
            DMA1_CH3_DST_MSW = 0xFFFF & (RxR1_DMA_address >> 16);
        }
//    add=(Uint16)RcvR_Sine;
//  	add = (add<<1) + 0x10000;
//    DMA1_CH3_DST_LSW = (Uint16)add;
//    DMA1_CH3_DST_MSW = 0xFFFF & (add >> 16);
        DMA_IFR = 0x0080;     // clear interrupt flags        
//        temp = DMA1_CH3_TC_MSW;
//	    temp |= 0x8000;
//	    DMA1_CH3_TC_MSW = temp;        
    }
}

TIMER:

void Timer0Init(void)
{

/* Timer0 Initialization */
// timer interval 10msec
// prescale = 0 (devide by 2)
// 100/2 = 50MHz ==> 20 nsec
// 10msec/20nsec = 500000 (0x7A120)

/* TIM0 EN | AutoReload disable | Prescale = 0(100/2 = 50MHz) ==> 20nsec */
*CPU_TIM0_CTRL = 0x8002; // autoReload
// *CPU_TIM0_CTRL = 0x8000; // disable autoReload

*CPU_TIM0_PLWR = 0xA120;
*CPU_TIM0_PHWR = 0x0007;

*CPU_TIM0_CLWR = 0x0000;
*CPU_TIM0_CHWR = 0x0000;

/* Clearing timer Aggregation register*/
*CPU_TIMINT_AGGR = 0x0007;

/* enable timer0 int flag*/
*CPU_TIM0_IER = 0x0001;
}

void StartTimer0(void)
{
/* Start the Timer 0*/
*CPU_TIM0_CTRL = *CPU_TIM0_CTRL | 0x0001;
}

interrupt void Timer_isr(void)
{

// clear timer int flag
IFR0 = IFR0&0x0010;

/* clear timer0 int flag*/
*CPU_TIM0_IER = 0x0001;

/* Clear Timer0 bit in Timer Aggregate register*/
*CPU_TIMINT_AGGR = *CPU_TIMINT_AGGR | 0x0001 ;

//StartTimer0();
}

DMA:

Uint16 set_dma1_ch0_i2s2_Lout(void)
{
Uint16 temp;
Uint32 add;

DMA1_CH0_TC_LSW = XMIT_BUFF_SIZE*2;

#if(AUTO_RELOAD ==1)
DMA1_CH0_TC_MSW = 0x3204; //src incre, destination fix, sync, auto
#else
DMA1_CH0_TC_MSW = 0x2204; //src incre, destination fix, sync, No auto
#endif

temp = DMA1_CH10_EVENT_SRC;
DMA1_CH10_EVENT_SRC = temp | 0x0001; // I2S2 transmit event

// if(fSineWave ==1)
// {
// add = (Uint32)XmitL_Sine_1K;
// }
// else
// {
// add = (Uint32)XmitL_Sine_2K;
// }
// add = (Uint32)XmitL_Sine_1K;
// add = (add<<1) + 0x10000; // change word address to byte address and add DARAM offset for DMA
DMA1_CH0_SRC_LSW = (Uint16)TxL1_DMA_address;

DMA1_CH0_SRC_MSW = 0xFFFF & (TxL1_DMA_address >> 16);

DMA1_CH0_DST_LSW = 0x2A08; // is20 transmit left data register lsw

// DMA starts
temp = DMA1_CH0_TC_MSW;
temp |= 0x8000;
DMA1_CH0_TC_MSW = temp;

return SUCCESS;
}

Uint16 set_dma1_ch1_i2s2_Rout(void)
{
Uint16 temp;
Uint32 add;

DMA1_CH1_TC_LSW = XMIT_BUFF_SIZE*2;
// DMA0_CH1_TC_LSW = 8;

#if(AUTO_RELOAD ==1)
DMA1_CH1_TC_MSW = 0x3204; //src incre, destination fix, sync, auto
#else
DMA1_CH1_TC_MSW = 0x2204; //src incre, destination fix, sync, No auto
#endif

temp = DMA1_CH10_EVENT_SRC;
DMA1_CH10_EVENT_SRC = temp | 0x0100; // I2S2 transmit event

// if(fSineWave ==1)
// {
// add = (Uint32)XmitR_Sine_1K;
// }
// else
// {
// add = (Uint32)XmitR_Sine_2K;
// }
// add = (Uint32)XmitR_Sine_1K;
// add = (add<<1) + 0x10000; //// change word address to byte address and add DARAM offset for DMA
DMA1_CH1_SRC_LSW = (Uint16)TxR1_DMA_address;

DMA1_CH1_SRC_MSW = 0xFFFF & (TxR1_DMA_address >> 16);

DMA1_CH1_DST_LSW = 0x2A0C; // is20 transmit right data register lsw

// DMA starts
temp = DMA1_CH1_TC_MSW;
temp |= 0x8000;
DMA1_CH1_TC_MSW = temp;

return SUCCESS;
}

Uint16 set_dma1_ch2_i2s2_Lin(void)
{
Uint16 temp;
Uint32 add;

DMA1_CH2_TC_LSW = XMIT_BUFF_SIZE*2;

#if(AUTO_RELOAD ==1)
DMA1_CH2_TC_MSW = 0x3084; //src fix, destination increase, sync, auto, int
#else
DMA1_CH2_TC_MSW = 0x2084; //src fix, destination increase,, No auto, int
#endif

temp = DMA1_CH32_EVENT_SRC;
DMA1_CH32_EVENT_SRC = temp | 0x0002; // I2S2 receive event

// add=(Uint16)RcvL_Sine;
// add = (add<<1) + 0x10000; //// change word address to byte address and add DARAM offset for DMA
DMA1_CH2_DST_LSW = RxL1_DMA_address;
DMA1_CH2_DST_MSW = 0xFFFF & (RxL1_DMA_address >> 16);

DMA1_CH2_SRC_LSW = 0x2A28; // is22 receive left data register lsw
DMA1_CH2_SRC_MSW = 0;

// CurrentRxL_DMAChannel =1;
// DMA starts
temp = DMA1_CH2_TC_MSW;
temp |= 0x8000;
DMA1_CH2_TC_MSW = temp;

return SUCCESS;
}

Uint16 set_dma1_ch3_i2s2_Rin(void)
{
Uint16 temp;
Uint32 add;

DMA1_CH3_TC_LSW = XMIT_BUFF_SIZE*2;

#if(AUTO_RELOAD ==1)
DMA1_CH3_TC_MSW = 0x3084; //src fix, destination increase, sync, auto , int
#else
DMA1_CH3_TC_MSW = 0x2084; //src fix, destination increase,, No auto, int
#endif

temp = DMA1_CH32_EVENT_SRC;
DMA1_CH32_EVENT_SRC = temp | 0x0200; // I2S2 receive event

// add=(Uint16)RcvR_Sine;
// add = (add<<1) + 0x10000;
DMA1_CH3_DST_LSW = (Uint16)RxR1_DMA_address;
DMA1_CH3_DST_MSW = 0xFFFF & (RxR1_DMA_address >> 16);

DMA1_CH3_SRC_LSW = 0x2A2C; // is22 receive right data register lsw
DMA1_CH3_SRC_MSW = 0;

// CurrentRxR_DMAChannel =1;
// DMA starts
temp = DMA1_CH3_TC_MSW;
temp |= 0x8000;
DMA1_CH3_TC_MSW = temp;

return SUCCESS;
}

void enable_dma_int(void)
{
DMA_MSK = 0x00F0; // enable all interrupts
DMA_IFR = 0xFFFF; // clear interrupt flags
}

interrupt void DMA_Isr(void)
{
Uint16 temp;//, dma_start;
Uint32 add;
temp = IFR0;
IFR0 = temp&0x0100;

temp = DMA_IFR;
// DMA_IFR = temp; // clear interrupt flags

if(temp&0x0010)
{
// // DMA TxL interrupt (channel 0)
if(CurrentTxL_DMAChannel ==1)
{
CurrentTxL_DMAChannel =2;
DMA1_CH0_SRC_LSW = (Uint16)TxL2_DMA_address;
DMA1_CH0_SRC_MSW = 0xFFFF & (TxL2_DMA_address >> 16);

}
else
{
CurrentTxL_DMAChannel =1;
DMA1_CH0_SRC_LSW = (Uint16)TxL1_DMA_address;
DMA1_CH0_SRC_MSW = 0xFFFF & (TxL1_DMA_address >> 16);
}
// add = (Uint32)XmitL_Sine_1K;
// add = (add<<1) + 0x10000; // change word address to byte address and add DARAM offset for DMA
// DMA1_CH0_SRC_LSW = (Uint16)add;
DMA_IFR = 0x0010; // clear interrupt flags
// temp = DMA1_CH0_TC_MSW;
// temp |= 0x8000;
// DMA1_CH0_TC_MSW = temp;
}
else if(temp&0x0020)
{
// DMA TxR interrupt (channel 1)
if(CurrentTxR_DMAChannel ==1)
{
CurrentTxR_DMAChannel =2;
DMA1_CH1_SRC_LSW = (Uint16)TxR2_DMA_address;
DMA1_CH1_SRC_MSW = 0xFFFF & (TxR2_DMA_address >> 16);
}
else
{
CurrentTxR_DMAChannel =1;
DMA1_CH1_SRC_LSW = (Uint16)TxR1_DMA_address;
DMA1_CH1_SRC_MSW = 0xFFFF & (TxR1_DMA_address >> 16);
}
// add = (Uint32)XmitR_Sine_1K;
// add = (add<<1) + 0x10000; //// change word address to byte address and add DARAM offset for DMA
// DMA1_CH1_SRC_LSW = (Uint16)add;
DMA_IFR = 0x0020; // clear interrupt flags
// temp = DMA1_CH1_TC_MSW;
// temp |= 0x8000;
// DMA1_CH1_TC_MSW = temp;
// temp=I2S2_W0_MSW_R;
}
else if(temp&0x0040)
{
// RunFilterForL =1;
// // DMA RxL interrupt (channel 2)
if(CurrentRxL_DMAChannel ==1)
{
// change DMA Tx SRC address
CurrentRxL_DMAChannel =2;

DMA1_CH2_DST_LSW = (Uint16)RxL2_DMA_address;
DMA1_CH2_DST_MSW = 0xFFFF & (RxL2_DMA_address >> 16);
}
else
{
CurrentRxL_DMAChannel =1;

DMA1_CH2_DST_LSW = (Uint16)RxL1_DMA_address;
DMA1_CH2_DST_MSW = 0xFFFF & (RxL1_DMA_address >> 16);
}
//// add=(Uint16)RcvL_Sine;
//// add = (add<<1) + 0x10000; //// change word address to byte address and add DARAM offset for DMA
// DMA1_CH2_DST_LSW = add;
// DMA1_CH2_DST_MSW = 0xFFFF & (add >> 16);
DMA_IFR = 0x0040; // clear interrupt flags
// temp = DMA1_CH2_TC_MSW;
// temp |= 0x8000;
// DMA1_CH2_TC_MSW = temp;
}
else if(temp&0x0080)
{
// RunFilterForR =1;
// // DMA RxR interrupt (channel 3)
if(CurrentRxR_DMAChannel ==1)
{
// change DMA Tx SRC address
CurrentRxR_DMAChannel =2;

DMA1_CH3_DST_LSW = (Uint16)RxR2_DMA_address;
DMA1_CH3_DST_MSW = 0xFFFF & (RxR2_DMA_address >> 16);
}
else
{
CurrentRxR_DMAChannel =1;

DMA1_CH3_DST_LSW = (Uint16)RxR1_DMA_address;
DMA1_CH3_DST_MSW = 0xFFFF & (RxR1_DMA_address >> 16);
}
// add=(Uint16)RcvR_Sine;
// add = (add<<1) + 0x10000;
// DMA1_CH3_DST_LSW = (Uint16)add;
// DMA1_CH3_DST_MSW = 0xFFFF & (add >> 16);
DMA_IFR = 0x0080; // clear interrupt flags
// temp = DMA1_CH3_TC_MSW;
// temp |= 0x8000;
// DMA1_CH3_TC_MSW = temp;
}
}

over 9 years ago

0 Vasantha K over 9 years ago

TI__Genius 12575 points

Hi,

You could refer to the attached CSL code . This would illustrate the DMA in Pingpong mode and timer in Auto reload mode.

Please note the example is a quick reference and no further support will be provided (wrt code).

Hope this helps you to proceed further.

Regards

Vasanth

csl_dma_pingpong_hwsync.c

#include "csl_dma.h"
#include "csl_intc.h"
#include <stdio.h>
#include <csl_general.h>
#include "csl_dma_pingpong_hwsync.h"
#include <csl_gpt.h>
#include <cslr_sysctrl.h>

#define CSL_DMA_BUFFER_SIZE 	1024
#define CSL_CHANNELS_PER_DMA	4
#define CSL_NUMBER_OF_DMA		4
#define CSL_TOTAL_DMA_CHANNELS	(CSL_CHANNELS_PER_DMA*CSL_NUMBER_OF_DMA)

/* Reference the start of the interrupt vector table */
extern void VECSTART(void);
/* Protype declaration for ISR function */
interrupt void dma_isr(void);

/* Declaration of the buffer */
#pragma DATA_SECTION(dmaSRCBuff,".srcbuffer")
#pragma DATA_SECTION(dmaDESTBuff,".dstbuffer")

/* Declaration of the buffer */
Uint16 dmaSRCBuff[CSL_DMA_BUFFER_SIZE];
Uint16 dmaDESTBuff[CSL_DMA_BUFFER_SIZE];
volatile int count =0;

/*Structure pointers for DMA*/
CSL_DMA_Handle 		dmaHandle;
CSL_DMA_Config 		dmaConfig;
CSL_DMA_Config 		getdmaConfig;
CSL_DMA_ChannelObj  dmaObj;

#ifdef CSL_SYSTEM_TIMER_TRIGGER
/*Structure pointers for TIMER*/
CSL_Handle    		hGpt;
CSL_Config 	  		hwConfig;
CSL_GptObj	  		gptObj;
#endif

Uint16	gDmaIntStatus[100];
Uint16 	gChanIntCount[16]={0, 0, 0, 0,
									0, 0, 0, 0,
									0, 0, 0, 0,
									0, 0, 0, 0};
#ifdef CSL_SYSTEM_TIMER_TRIGGER
Uint16	gTimerIntStatus[100];
Uint16	gTimerIntCount[3]={0,0,0};
#endif

volatile Uint16	dma_isr_index = 0;
volatile Uint16	timer_isr_index = 0;


interrupt void dma_isr(void)
{
	CSL_SysRegsOvly	sysCtrlRegs;

	sysCtrlRegs = CSL_SYSCTRL_REGS;

	/*Log status*/
	gDmaIntStatus[dma_isr_index] = sysCtrlRegs->DMAIFR;

	/*Clear */
	sysCtrlRegs->DMAIFR = gDmaIntStatus[dma_isr_index];

	if(0x0001 & gDmaIntStatus[dma_isr_index]) /*CHAN0*/
		gChanIntCount[0]++;

	if(0x0002 & gDmaIntStatus[dma_isr_index]) /*CHAN1*/
		gChanIntCount[1]++;

	if(0x0004 & gDmaIntStatus[dma_isr_index]) /*CHAN2*/
		gChanIntCount[2]++;

	if(0x0008 & gDmaIntStatus[dma_isr_index]) /*CHAN3*/
		gChanIntCount[3]++;


	if(0x0010 & gDmaIntStatus[dma_isr_index]) /*CHAN4*/
		gChanIntCount[4]++;

	if(0x0020 & gDmaIntStatus[dma_isr_index]) /*CHAN5*/
		gChanIntCount[5]++;

	if(0x0040 & gDmaIntStatus[dma_isr_index]) /*CHAN6*/
		gChanIntCount[6]++;

	if(0x0080 & gDmaIntStatus[dma_isr_index]) /*CHAN7*/
		gChanIntCount[7]++;


	if(0x0100 & gDmaIntStatus[dma_isr_index]) /*CHAN8*/
		gChanIntCount[8]++;

	if(0x0200 & gDmaIntStatus[dma_isr_index]) /*CHAN9*/
		gChanIntCount[9]++;

	if(0x0400 & gDmaIntStatus[dma_isr_index]) /*CHAN10*/
		gChanIntCount[10]++;

	if(0x0800 & gDmaIntStatus[dma_isr_index]) /*CHAN11*/
		gChanIntCount[11]++;


	if(0x1000 & gDmaIntStatus[dma_isr_index]) /*CHAN12*/
		gChanIntCount[12]++;

	if(0x2000 & gDmaIntStatus[dma_isr_index]) /*CHAN13*/
		gChanIntCount[13]++;

	if(0x4000 & gDmaIntStatus[dma_isr_index]) /*CHAN14*/
		gChanIntCount[14]++;

	if(0x8000 & gDmaIntStatus[dma_isr_index]) /*CHAN15*/
		gChanIntCount[15]++;

	/*Increment logger pointer*/
	dma_isr_index++;
}

#ifdef CSL_SYSTEM_TIMER_TRIGGER
interrupt void timer_isr(void)
{
	CSL_SysRegsOvly	sysCtrlRegs;

	sysCtrlRegs = CSL_SYSCTRL_REGS;

	/*Log status*/
	gTimerIntStatus[timer_isr_index] = sysCtrlRegs->TIAFR;

	/*Clear */
	sysCtrlRegs->TIAFR = gTimerIntStatus[timer_isr_index];

	if(0x0001 & gTimerIntStatus[timer_isr_index]) /*TIMER0*/
		gTimerIntCount[0]++;

	if(0x0002 & gTimerIntStatus[timer_isr_index]) /*TIMER1*/
		gTimerIntCount[1]++;

	if(0x0004 & gTimerIntStatus[timer_isr_index]) /*TIMER2*/
		gTimerIntCount[2]++;

	/*Increment logger pointer*/
	timer_isr_index++;
}
#endif

void validate_dma_after_run(void)
{
		/* validation for set and get config parameter */
		if((dmaConfig.autoMode) != (getdmaConfig.autoMode))
		{
			printf(" Mode not matched\n");
		}

		if(((dmaConfig.burstLen) != (getdmaConfig.burstLen)))
		{
			printf(" Burst length not matched\n");
		}

		if(((dmaConfig.trigger) != (getdmaConfig.trigger)))
		{
			printf(" Triger type not matched\n");
		}

		if(((dmaConfig.dmaEvt) != (getdmaConfig.dmaEvt)) )
		{
			printf(" Event not matched\n");
		}

		if(((dmaConfig.dmaInt) != (getdmaConfig.dmaInt)))
		{
			printf(" Interrupt state not matched\n");
		}

		if(((dmaConfig.chanDir) != (getdmaConfig.chanDir)))
		{
			printf(" Direction read or write not matched\n");
		}

		if(((dmaConfig.trfType) != (getdmaConfig.trfType)))
		{
			printf(" Transfer type not matched\n");
		}

		if(((dmaConfig.dataLen) != (getdmaConfig.dataLen)))
		{
			printf(" data length of transfer not matched\n");
		}

		if(((dmaConfig.srcAddr) != (getdmaConfig.srcAddr)))
		{
			printf(" Source address not matched\n");
		}

		if(((dmaConfig.destAddr) != (getdmaConfig.destAddr)))
		{
			printf(" Destination address not matched\n");
		}
}

CSL_Status csl_dma_4ch_hw_test(void)
{


	CSL_Status 			status;
	Uint16   			chanNumber;
	Uint16   			i;

	printf("\n DATA TRANSFER IS FROM DARAM TO SARAM\n");
	printf("\n BURST MODE IS SET TO 16 DOUBLE WORDS\n");
	printf("\n TIMER0 IS USED TO GENERATE SYNC\n");

#ifdef CSL_SYSTEM_ENABLE_PINGPONG
	dmaConfig.pingPongMode = CSL_DMA_PING_PONG_ENABLE;
#else
	dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
#endif

	dmaConfig.autoMode     = CSL_DMA_AUTORELOAD_DISABLE;
	dmaConfig.burstLen     = CSL_DMA_TXBURST_16WORD;
#ifdef CSL_SYSTEM_TIMER_TRIGGER
	dmaConfig.trigger      = CSL_DMA_EVENT_TRIGGER;
	dmaConfig.dmaEvt       = CSL_DMA_EVT_TIMER1;
#else
	dmaConfig.trigger      = CSL_DMA_SOFTWARE_TRIGGER;
	dmaConfig.dmaEvt       = CSL_DMA_EVT_NONE;
#endif
	dmaConfig.dmaInt       = CSL_DMA_INTERRUPT_ENABLE;
	dmaConfig.chanDir      = CSL_DMA_READ;
	dmaConfig.trfType      = CSL_DMA_TRANSFER_MEMORY;
	dmaConfig.dataLen      = CSL_DMA_BUFFER_SIZE * 2;
	dmaConfig.srcAddr      = (Uint32)dmaSRCBuff;
	dmaConfig.destAddr     = (Uint32)dmaDESTBuff;

	IRQ_globalDisable();

	IRQ_clearAll();

	IRQ_disableAll();

	/*Clear IFR*/
	CSL_SYSCTRL_REGS->DMAIFR = 0xFFFF;
	/*Set masks*/
	CSL_SYSCTRL_REGS->DMAIER = 0xFFFF;

	IRQ_setVecs((Uint32)&VECSTART);
	IRQ_clear(DMA_EVENT);

	IRQ_plug (DMA_EVENT, &dma_isr);

	IRQ_enable(DMA_EVENT);
	IRQ_globalEnable();

    status = DMA_init();
    if (status != CSL_SOK)
    {
        printf(" DMA_init() Failed \n");
		return(status);
    }
#ifdef CSL_SYSTEM_TIMER_TRIGGER
	/*Register the TIMER Handler and plug the ISR vector*/
	status = Register_Timer();
	if(status != CSL_SOK)
	{
		printf(" Timer Handler Register Failed!!\n");	
		return(status);	
	}
#endif
	
	for( chanNumber = 0; chanNumber < CSL_TOTAL_DMA_CHANNELS; chanNumber++)
	{
	    count = 0;

		for(i = 0; i< CSL_DMA_BUFFER_SIZE; i++)
		{
			dmaSRCBuff[i]  = i;
			dmaSRCBuff[i]  <<= 6;
			dmaSRCBuff[i]  |= i;
			dmaDESTBuff[i] = 0x0000;
		}

	    printf("\n Test for DMA Channel No : %d \t", chanNumber);

		dmaHandle = DMA_open((CSL_DMAChanNum)chanNumber,&dmaObj, &status);
        if (dmaHandle == NULL)
        {
            printf(" DMA_open() Failed \n");
            break;
        }

		status = DMA_config(dmaHandle, &dmaConfig);
        if (status != CSL_SOK)
        {
            printf(" DMA_config() Failed \n");
            break;
        }

		status = DMA_getConfig(dmaHandle, &getdmaConfig);
        if (status != CSL_SOK)
        {
            printf(" DMA_getConfig() Failed \n");
            break;
        }
		/*Start DMA*/
		status = DMA_start(dmaHandle);
        if (status != CSL_SOK)
        {
            printf(" DMA_start() Failed \n");
            break;
        }
#ifdef CSL_SYSTEM_TIMER_TRIGGER
		for(i = 0; i < 100; i++){;}
		/*Configure and Run TIMER */
		status = config_timerevent(TIMER);
		if(status != CSL_SOK)
		{
			printf(" Timer Configure Failed!!\n");
			break ;
		}
#endif
 	    //while(count != 1);
#ifdef CSL_SYSTEM_ENABLE_PINGPONG
		while(CSL_SOK != CSL_SYSTEM_checkPingPongStatus(dmaHandle))
#else
		while(CSL_SOK != CSL_SYSTEM_checkDmaStatus(chanNumber))
#endif

#ifdef CSL_SYSTEM_TIMER_TRIGGER
		/* Stop The Timer */
		status = GPT_stop(hGpt);
		if(CSL_SOK != status)
		{
			printf(" Timer0 Stop Failed \n");
			break;
		}
		/* Reset the timer count to zero */
		status = GPT_reset(hGpt);
		if(CSL_SOK != status)
		{
			printf(" Timer0 Reset Failed \n");
			break;
		}
		/* Close the GPT module */
		status = GPT_close(hGpt);
		if(CSL_SOK != status)
		{
			printf(" Timer0 Close Failed\n");
			break;
		}
#endif
		status = DMA_close(dmaHandle);
        if (status != CSL_SOK)
        {
            printf(" DMA_close() Failed \n");
            break;
        }

        status = DMA_reset(dmaHandle);
        if (status != CSL_SOK)
        {
            printf(" DMA_reset() Failed \n");
            break;
        }

		/* validation for set and get config parameter */
		validate_dma_after_run();

		for(i = 0; i < CSL_DMA_BUFFER_SIZE; i ++)
		{
			if(dmaSRCBuff[i] != dmaDESTBuff[i])
			{
				printf(" Buffer miss matched at position %d\n",i);
				break;
			}
		}

		if(i == CSL_DMA_BUFFER_SIZE)
		{
			printf(" Buffers Matched\n");
		}
		else
			break;
	}

	IRQ_clearAll();
	IRQ_disableAll();
	IRQ_globalDisable();
	if(dma_isr_index == CSL_TOTAL_DMA_CHANNELS)
		return (CSL_SOK);
	else
		return (CSL_ESYS_FAIL);
}

/////INSTRUMENTATION FOR BATCH TESTING -- Part 1 --
/////  Define PaSs_StAtE variable for catching errors as program executes.
/////  Define PaSs flag for holding final pass/fail result at program completion.
    volatile Int16 PaSs_StAtE = 0x0001; // Init to 1. Reset to 0 at any monitored execution error.
    volatile Int16 PaSs = 0x0000; // Init to 0.  Updated later with PaSs_StAtE when and if
/////                                  program flow reaches expected exit point(s).
/////

void main(void)
{
	CSL_Status    		result;
		
	printf("\n DMA PING-PONG WITH HW SYNC MODE TEST!\n");
	result = csl_dma_4ch_hw_test();
	if(result == CSL_SOK)
	{
		printf("\n\n DMA PING-PONG WITH HW SYNC MODE TEST PASSED!!\n");
	}
	else
	{
		printf("\n\n DMA HW PING-PONG WITH SYNC MODE TEST FAILED!!\n");
		PaSs_StAtE = 0x0000; // Was intialized to 1 at declaration.
	}

   /////INSTRUMENTATION FOR BATCH TESTING -- Part 3 --
   /////  At program exit, copy "PaSs_StAtE" into "PaSs".
        PaSs = PaSs_StAtE; //If flow gets here, override PaSs' initial 0 with
   /////                   // pass/fail value determined during program execution.
   /////  Note:  Program should next exit to C$$EXIT and halt, where DSS, under
   /////   control of a host PC script, will read and record the PaSs' value.
   /////

}

#ifdef CSL_SYSTEM_TIMER_TRIGGER
static CSL_Status Register_Timer(void)
{
	CSL_Status 	status;
	CSL_SysRegsOvly	sysCtrlRegs;

	sysCtrlRegs = CSL_SYSCTRL_REGS;
	status 		= CSL_SOK;

	/*Disable cpu interrupts*/
	IRQ_globalDisable();

	/*Clear any pending interrupts*/
//	IRQ_clearAll();

	/*Disable all interrupts*/
//	IRQ_disableAll();

	/*Clear old*/
	sysCtrlRegs->TIAFR = 0x0007;

	IRQ_setVecs((Uint32)&VECSTART);
	IRQ_clear(TINT_EVENT);

	/*Register ISR to IVT*/
	IRQ_plug(TINT_EVENT, &timer_isr);

	/*Enable event*/
	IRQ_enable(TINT_EVENT);

	/*Enable cpu interrupts*/
	IRQ_globalEnable();

	return status;
}

CSL_Status config_timerevent(unsigned char timer_no)
{
	/*
	CSL_Handle    hGpt;
	CSL_Config 	  hwConfig;
	CSL_GptObj	  gptObj;
	*/
	CSL_Status 	  status;
	//Uint32    sysClk;

	status   = 0;

	//sysClk = getSysClk();

	/* Open the CSL GPT modules */
	hGpt = GPT_open ((CSL_Instance)timer_no, &gptObj, &status);
	if((NULL == hGpt) || (CSL_SOK != status))
	{
		printf(" Timer %d Open Failed\n",timer_no);
		return (CSL_ESYS_FAIL);
	}


	/* Reset the GPT modules */
	status = GPT_reset(hGpt);
	if(CSL_SOK != status)
	{
		printf(" Timer %d Reset Failed\n",timer_no);
		return (CSL_ESYS_FAIL);
	}

	/* Configuring the GPT0 */
	//hwConfig.autoLoad 	 = GPT_AUTO_DISABLE;
	hwConfig.autoLoad 	 = GPT_AUTO_ENABLE;
	hwConfig.ctrlTim 	 = GPT_TIMER_ENABLE;
	hwConfig.preScaleDiv = GPT_PRE_SC_DIV_1;
	hwConfig.prdLow 	 = 0x00FF;
	hwConfig.prdHigh 	 = 0x0000;

	/* Configure the GPT0 module */
	status =  GPT_config(hGpt, &hwConfig);
	if(CSL_SOK != status)
	{
		printf(" Timer %d Config Failed\n",timer_no);
		return (CSL_ESYS_FAIL);
	}
	/* Start the Timer */
	GPT_start(hGpt);
	printf(" Timer %d is now running\n",timer_no);
	return (status);
}
#endif

#ifdef CSL_SYSTEM_ENABLE_PINGPONG
CSL_Status CSL_SYSTEM_checkPingPongStatus(CSL_DMA_Handle dmaHandle)
{
	CSL_Status 	status;
	Uint16		*intCount;

	status 		= CSL_ESYS_FAIL;
	intCount 	= &gChanIntCount[dmaHandle->chanNum];

	if(*intCount ==2)
	{
		printf(" Ping & Pong came quickly for DMA Channel-%d\n",
			dmaHandle->chanNum);
		*intCount	= 0;
		dma_isr_index-=1;
		status		= CSL_SOK;
	}

	if(*intCount ==1)
	{
		if ((DMA_getLastTransferType (dmaHandle, &status)) == 1)
		{
			printf(" Pong %s Completed for DMA Channel-%d\n",
				dmaHandle->chanDir?"Write":"Read", dmaHandle->chanNum);
		}
		else
		{
			printf(" Ping %s Completed for DMA Channel-%d\n",
				dmaHandle->chanDir?"Write":"Read", dmaHandle->chanNum);
		}
		status 		= CSL_SOK;
		*intCount 	= 0;
	}

	return status;

}
#else

CSL_Status CSL_SYSTEM_checkDmaStatus(Uint16 chanNum)
{
	CSL_Status 	status;
	Uint16		*intCount;

	status 		= CSL_ESYS_FAIL;
	intCount 	= &gChanIntCount[chanNum];

	//while(*intCount !=1);

	if(*intCount ==1)
	{
		printf(" Transfer Completed for DMA Channel-%d\n", chanNum);
		*intCount = 0;
		status = CSL_SOK;
	}

	return status;
}
#endif

0 Bill Finger over 9 years ago

Genius 3735 points

I don't see where you've installed the ISRs into the vector table. Does your timer work without the DMA?

Regards,
Bill

0 Nitin Chavan1 over 9 years ago in reply to Bill Finger

Prodigy 130 points

I am using the CSL api's to configure the timer and dma interrupt. I am using the USB isr. The DMA and USB ISRs are working fine...for testing I have enabled timer ISR , DMA ISR and USB ISR in USB config function. I am copying the USB initialize function below, in the same code the dma initialization and timer initialization happens.

/**
* \brief Tests USB interrupt mode operation
*
* \param none
*
* \return Test result
*/
CSL_Status CSL_usbIntcTest(void)
{
CSL_IRQ_Config config;
CSL_Status result;
Uint16 eventMask;

result = CSL_USB_TEST_FAILED;

*(ioport volatile int *)0x1c02 = 0x0;
*(ioport volatile int *)0x1c03 = 0x0;

usbConfig.opMode = CSL_USB_OPMODE_POLLED;
usbConfig.devNum = CSL_USB0;
usbConfig.maxCurrent = CSL_USB_MAX_CURRENT;
usbConfig.appSuspendCallBack = (CSL_USB_APP_CALLBACK)CSL_suspendCallBack;
usbConfig.appWakeupCallBack = (CSL_USB_APP_CALLBACK)CSL_selfWakeupCallBack;
usbConfig.startTransferCallback = CSL_startTransferCallback;
usbConfig.completeTransferCallback = CSL_completeTransferCallback;

hEpObjArray[0] = &usbCtrlOutEpObj;
hEpObjArray[1] = &usbCtrlInEpObj;
hEpObjArray[2] = &usbBulkOutEpObj;
hEpObjArray[3] = &usbBulkInEpObj;
// IRQ_globalDisable();
/* Set the interrupt vector start address */
IRQ_setVecs((Uint32)(&VECSTART));

/* Enable CPU Interrupts */

/*********************** Added by vivek for timer interrupt from CSL ********/
/* Enable CPU Interrupts */
/********************* END ***********************************************/

/* Plug the USB Isr into vector table */
config.funcAddr = &usb_isr;
IRQ_plug(USB_EVENT, config.funcAddr);

/* Enable USB Interrupts */
IRQ_enable(USB_EVENT);

config.funcAddr = &tim_isr;
IRQ_plug(TINT_EVENT, config.funcAddr);

// /* Enable USB Interrupts */
IRQ_enable(TINT_EVENT);

/* Plug the DMA Isr into vector table */

config.funcAddr = &DMA_Isr;
IRQ_plug(DMA_EVENT, config.funcAddr);

IRQ_enable(DMA_EVENT);

IRQ_globalEnable();

setDMA_address();
enable_dma_int();
Timer0Init();
StartTimer0();

set_dma1_ch0_i2s2_Lout();
set_dma1_ch1_i2s2_Rout();
set_dma1_ch2_i2s2_Lin();
set_dma1_ch3_i2s2_Rin();

/* Initialize the USB module */
status = USB_init(&usbConfig);
if(status != CSL_SOK)
{
#if PRINT_DEBUG
printf("USB init failed\n");
#endif
return(result);
}

/* Reset the USB device */
status = USB_resetDev(CSL_USB0);
if(status != CSL_SOK)
{
#if PRINT_DEBUG
printf("USB Reset failed\n");
#endif
return(result);
}

/* Initialize the Control Endpoint OUT 0 */
eventMask = (CSL_USB_EVENT_RESET | CSL_USB_EVENT_SETUP |
CSL_USB_EVENT_SUSPEND | CSL_USB_EVENT_RESUME |
CSL_USB_EVENT_RESET | CSL_USB_EVENT_EOT);

status = USB_initEndptObj(CSL_USB0, hEpObjArray[0],
CSL_USB_OUT_EP0,CSL_USB_CTRL,
CSL_USB_EP0_PACKET_SIZE, eventMask, NULL);
if(status != CSL_SOK)
{
#if PRINT_DEBUG
printf("USB End point init failed\n");
#endif
return(result);
}

/* Initialize the Control Endpoint IN 0 */
status = USB_initEndptObj(CSL_USB0, hEpObjArray[1], CSL_USB_IN_EP0,
CSL_USB_CTRL, CSL_USB_EP0_PACKET_SIZE,
CSL_USB_EVENT_EOT, NULL);

/***************************************************************************/
if(status != CSL_SOK)
{
#if PRINT_DEBUG
printf("USB End point init failed\n");
#endif
return(result);
}

/********************************* vivek **********************************************/
// /* Initialize the Bulk Endpoint IN 1 */
// eventMask = (CSL_USB_EVENT_RESET | CSL_USB_EVENT_EOT);
// status = USB_initEndptObj(CSL_USB0, hEpObjArray[2], CSL_USB_IN_EP1,
// CSL_USB_BULK, CSL_USB_EP1_PACKET_SIZE_FS,
// eventMask, NULL);
// if(status != CSL_SOK)
// {
// printf("USB End point init failed\n");
// return(result);
// }

/* Initialize the Bulk Endpoint IN 4 */
eventMask = (CSL_USB_EVENT_RESET | CSL_USB_EVENT_EOT);
status = USB_initEndptObj(CSL_USB0, hEpObjArray[2], CSL_USB_IN_EP4,
CSL_USB_BULK, CSL_USB_EP4_PACKET_SIZE_FS,
eventMask, NULL);
if(status != CSL_SOK)
{
#if PRINT_DEBUG
printf("USB End point init failed\n");
#endif
return(result);
}
/****************************************************************************************************/

/* Initialize the Bulk Endpoint OUT 2 */
status = USB_initEndptObj(CSL_USB0, hEpObjArray[3], CSL_USB_OUT_EP2,
CSL_USB_BULK, CSL_USB_EP2_PACKET_SIZE_FS,
CSL_USB_EVENT_EOT, NULL);
if(status != CSL_SOK)
{
#if PRINT_DEBUG
printf("USB End point init failed\n");
#endif
return(result);
}

/* Set the parameters */
status = USB_setParams(CSL_USB0, hEpObjArray, FALSE);
if(status != CSL_SOK)
{
#if PRINT_DEBUG
printf("USB Set params failed\n");
#endif
return(result);
}

/* Connect the USB device */
status = USB_connectDev(CSL_USB0);
if(status != CSL_SOK)
{
#if PRINT_DEBUG
printf("USB Connect failed\n");
#endif
return(result);
}

deviceDescPtr = (Uint16 *)deviceDesc;
cfgDescPtr = (Uint16 *)cfgDesc;
strDescPtr = (Uint16 *)strDesc;
USB_CONNECTED = 1; // Added by vivek to set USB connection FLAG

while(1)
{
if(USB_CONNECTED ==0)
{
while(CSL_FEXT(usbRegisters->DEVCTL, USB_DEVCTL_VBUS) !=
CSL_USB_DEVCTL_VBUS_ABOVEVBUSVALID);

printf("USB Cable Connection Detected!!\n");

usbDevDisconnect = FALSE;
USB_connectDev(CSL_USB0);
USB_CONNECTED = 1;
}

}

while(stopRunning != TRUE)
{
if ((usbDevDisconnect == TRUE) &&
(CSL_FEXT(usbRegisters->DEVCTL, USB_DEVCTL_VBUS) !=
CSL_USB_DEVCTL_VBUS_ABOVEVBUSVALID))
{
printf("\nUSB Cable Disconnected!!\n");

while(CSL_FEXT(usbRegisters->DEVCTL, USB_DEVCTL_VBUS) !=
CSL_USB_DEVCTL_VBUS_ABOVEVBUSVALID);

printf("USB Cable Connection Detected!!\n");

usbDevDisconnect = FALSE;
USB_connectDev(CSL_USB0);
}

}

result = CSL_USB_TEST_PASSED;
return(result);
}

0 Bill Finger over 9 years ago in reply to Nitin Chavan1

Genius 3735 points

Mr. Chavan,

I would delete these lines from your Timer ISR:

// clear timer int flag
IFR0 = IFR0&0x0010;

/* clear timer0 int flag*/
*CPU_TIM0_IER = 0x0001;

They are not required.

Regards,

Bill

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C5515 timer and DMA issue