• Locked Locked
  • Replies 1 reply
  • Subscribers 102 subscribers
  • Views 448 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

no reasonable clockout's on highend 55xx at all

Lars Dittmar
Prodigy 190 points

only 6 devides power of 2 on IIS and  16 '2 on MCSPI, No TOUT on any timer, no clkstp on McBsp...  You want a simple sampleclock but in a wide range 1k-500k and specific clock rates for such an SPI ADC on  the 55xx ass-backwards DSP?  Take the long way around? Sync a DMA with the Timer_int, send a double memory cell 1/0 to a GPIO or what? And the resulting jitter? Has anyone a better ass-backwards? Another solution: wait for the 5537 but it is not publically available.

See SLAA342. Can anyone rewire it for this unbelievable hightec_device?

Thanks

  • TI__Genius 12575 points

    Hi,

    Not sure whether I completely understood your post. please ask us back if you need more information than provided below.

    With respect to C5517 device , there exists a clock gating feature for McBSP. McBSP clock gate control bit.

    0 McBSP clock is active.

    1 McBSP clock is disabled.

    Yes, there no TOUT for any of the timers in this device and  would like to clarify that CLKOUT is recommended for debug purpose only in the data manual under CLKOUT Pin section. This pin has not been characterized as a clock source like rise/fall time and duty cycle. System level verification is recommended for specific usage.

    SAR clock can produce the low frequency clock  SAR A/D Clock Frequency = (System Clock Frequency) / (SystemClkDivisor + 1) where . This clock can be clocked out. but the above mentioned clock out contraint would still apply for this.

    With respect to McSPI - In master mode, the baud rate of the SPI serial clock is programmable using the internal McSPI module functional clock, McSPI Reference Clock. The McSPI Reference Clock is divided down from the system clock by two dividers programmable through the McSPI Functional Clock Divide Register, 0x1C3C.

    1. McSPI Reference Clock Pre-divider that divides by 1, 2, or 4

    2. McSPI Reference Clock Divider that divides from 1, 2, 4, 6, 8, to 30.

    On I2S -  the I2S module generates these clocks by dividing the system clock by a value calculated from the CLKDIV and FSDIV fields programmed in the I2SSRATE register.

    I2Sn_CLK = SystemClock / (2 power CLKDIV+1)

    I2Sn_FS = I2Sn_CLK / (2 power FSDIV+3)

    Where The system clock to the I2S is divided down by the configured value to generate the bit clock. No effect when configured as slave. Where CLKDIV can be configured for max value of 7 which is divide by 256.

    Divider to generate I2S frame sync clock. The I2S_BCLK is divided down by the configured value to generate the frame sync clock. No effect when configured as slave.Here FSDIV can be configured to max value of 5 which is divide by 256 value.

    Hope the above information helps.

    Regards

     Vasanth