• State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 102 subscribers
  • Views 736 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C5510 EMIF Speed

MARK LO
Intellectual 320 points

How do I change the C5510 EMIF speed for interfacing with the async SRAM?  For EMIF async interface, I believe EMIF runs at CPU speed.  Do I can change the CPU speed by using the PLL_conig & PLL_setFreq functions in the CSL?

  • 0
    TI__Mastermind 23785 points
    Since you are using async memory, can you use the programmable hold period to adjust the timing instead of slowing down the CPU frequency?
    Regards.
  • 0 in reply to Steve Tsang
    Intellectual 320 points
    but is it possible to change the EMIF speed for async memory?
  • 0 in reply to MARK LO
    TI__Mastermind 23785 points
    The EMIF async operation in relationship to internal CPU clock is by # of clock cycles. The internal CPU clock frequency is is generated by multipling the CLKIN with a synthesis factor determined by PLL_MULT and PLL_DIV fields in the clock mode register. So, in a sense, you can change the EMIF physical time by changing the internal CPU clock frequency; however, the # of clock cycle remains the same.
    Regards.
  • 0 in reply to Steve Tsang
    Intellectual 320 points
    200MHz CPU is 5nSec per clock cycle. Targeting async SRAM an access time of 550nSec renders 550nSec/5nSec = 110 clock cycles. Account for the ‘cable lengths’ and give time for signals to ‘settle’, yields the spread of those 110 clock cycles (between setup, strobe, hold) to meet timing. We determined we needed about 102 cycles for the read strobe and 86 cycles for the write strobe, but according to the chip set library (CSL) manual, the max value can only be 63. That's why we want to change the CPU clock. Another other way to do?
  • 0 in reply to MARK LO
    TI__Genius 12790 points

    Mark,

    As Steve mentioned in previous post, the EMIF clock input comes from CPU clock, there is no way to divide the CPU clock just for the EMIF, in effect sending it a lower source clock.

    May i ask what SRAM you are using?  550ns time is < 2MHz.

    Also as Steve Mentions, the only way to get the EMIF access cycle to slow down is to reduce the main CPU clock.  ie working backwards, to get a 2MHz access cycle, you'd need to use max SETUP/STROBE/HOLD settings, which gives 83 clock cycles ... you'd have to run your main DPS clock at ~24MHz.  I'm not sure this is feasible but depends on your needs.

    Regards,
    Marc

  • 0 in reply to pathfinder
    Intellectual 320 points
    If it is feasible, do I use the PLL_Config and PLL_setFreq functions from the CSL to change the clock frequnecy?
    What is the difference between PLL_Config and PLL_setFreq? I see both functions set the freq mult and div. Is there a reference guide on the C5510DSP PLL?