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A question about the transmit clock polarity of C5509's McBSP working as SPI Slave

Oliver Chen
Intellectual 725 points
Other Parts Discussed in Thread: TMS320VC5501

Dear All,

I've a question about the transmit clock polarity of C5509's McBSP2 working as SPI Slave.

I'd like to configure my C5509A's McBSP2 as SPI Slave and set the polarity of its CLKX & CLKR to what described in:

Figure 6−3. SPI Transfer With CLKSTP = 11b (clock delay), CLKXP = 0, CLKRP = 1 of TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (SPRU592E).

In such configuration, I expect:

1. McBSP2's Receiver samples data on clock's rising edge and

2. McBSP2's Transmitter transmits date on clock's falling edge.

I believe that Receiver works as what I expected because in my program I can correctly receives the data from SPI Master. 

However, the Transmitter clock's polarity is not what I expected: It transmits data on clock's RISING edge instead of on falling edge. You should be able to see this in the following screen capture (MISO toggles right after SCK's positive edge):

By checking the register in CCS I believe the following register settings are what I expected:

1. CLKSTP = 11b

2. CLKXP = 0

3. CLKRP = 1

I'll appreciate if anyone could advise why transmitter's clock polarity is not what I expected.

Thanks in advance!

Regards,

Oliver

  • 0
    TI__Genius 12575 points

    Hi,

      Can you Turn on  the DX-pin delay enabler (DXENA) bit  in SPCR1 register and check.

    Regards

     Vasanth

  • 0 in reply to Vasantha K
    Intellectual 725 points

    Dear Vasanth,

    First thank you for your reply and suggestion.

    I've set SPCR1's DXENA (Bit7 of the register at 0x003005 in the screen capture below) to 1 and tried again. However, this symptom remain unchanged. The waveform is the same (MISO toggles right after the positive edge of SCK).

    And, according to TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Ref. Guide (SPRU592E), turning DXENA on will delay the first bit, not alter the clock polarity of transmitted data.

    Any comment?

    Regards,

    Oliver

  • 0 in reply to Oliver Chen
    TI__Genius 12575 points

    Hi Oliver,

    Thanks for the update.

    I need one more input from you. Can you configure CLKXP to 1 instead of Zero and check whether the transmit happens at falling edge. Let's ignore delay for time being.

    Regards

     Vasanth

  • 0 in reply to Vasantha K
    Intellectual 725 points

    Dear Vasanth,

    If CLKXP is set to 1 then MISO will toggle right after negative edge of SCK.

    Unfortunately, there is a side effect: McBSP Receiver will incorrectly sample the MOSI signal.

    In the waveform above, the first byte of MOSI should be 0x0B. When CLKXP is set to 0, my FW will correctly get this data as 0x0B. However, if CLKXP is set to 1, then FW will get it as 0x17.

    Any idea about this weird side effect?

    Regards,

    Oliver

  • 0 in reply to Oliver Chen
    TI__Genius 12575 points

    Hi Oliver,

      I also meant to program clock stop to 'b10 that is Clock stop mode, without clock delay. (Not sure whether clock delay is a must for your system to work)

      Could you confirm with the above configuration. 

    Regards

     Vasanth

     

  • 0 in reply to Vasantha K
    Intellectual 725 points

    Dear Vasanth,

    Setting "CLKSTP = 10 and CLKXP = 1" produces the same results as "CLKSTP = 11 and CLKXP = 0". In both configurations

    my FW can correctly get the data from SPI Master and transmit data on the undesired (rising) SCK edge.

    Any other thought?

    Regards,

    Oliver

  • 0 in reply to Oliver Chen
    Intellectual 725 points

    Dear Vasanth,

    I manage to build an SPI Master with 1MHz SPI clock and have it to send the same data (You can see them on MOSI: 0x0B, 0x00, 0x00, 0x00, 0x00) to C5509A. In the waveform below, you can see that McBSP transmitter toggles MISO right after the FALLING edge of SCK. Here CLKSTP=10b, CLKXP=1 & CLKRP=0.

    With exactly the same FW, I use the original SPI Master, which has 17MHz SPI clock, do this experiment again and find MISO toggles right after the RISING edge of SCK. Please check the waveform below.

    Since the difference between these two experiments are only the SCK frequency (1MHz vs. 17MHz), I'm wondering if this is a timing issue?

    (My C5509A runs at 192MHz, if you are interested)

    Regards,

    Oliver

  • 0 in reply to Oliver Chen
    TI__Genius 12575 points

    Hi Oliver,

    Yes, Suggest you to confirm all the timing parameters as specified in the C5509A datasheet section 5.14.3 are met.

    For McBSP as SPI slave the minimum cycle time CLKX needs to be 16P where P = 1/cpu clock frequency. In addition to CPU frequency, the maximum operating frequency of the serial port also depends on meeting the rest of the switching characteristics and timing requirements parameters specified.

    Regards

     Vasanth

  • 0 in reply to Vasantha K
    Intellectual 725 points

    Dear Vasanth,

    OK, I understand. The root cause of this symptom is the 17MHz SCK from SPI Master exceeds the highest frequency (12MHz) that my C5509A running at 192MHz can support.

    Thanks for your great help and efforts!

    Regards,

    Oliver

  • 0 in reply to Oliver Chen
    TI__Genius 12575 points

    Hi Oliver,

      Yes that's correct and I am glad it resolved.

    Regards

     Vasanth