ezdspC5535 both timer flags (T0FLAG & T1FLAG of TIAFR) are getting set even though time periods are different

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *  ============================================================================
 */

/** @file csl_gpt_example.c
 *
 *  @brief Example test code to verify the CSL GPT module functionality
 *
 * \page    page4  GPT EXAMPLE DOCUMENTATION
 *
 * \section GPT   GPT EXAMPLE
 *
 * \subsection GPTx    TEST DESCRIPTION:
 *		This test code verifies the functionality of the CSL GPT (General
 * Purpose Timer) module. GPT module of C5505/C5515 DSP is used to provide
 * interrupts to the CPU to schedule periodic tasks or a delayed task.
 * GPT can be configured with a counter and pre-scaler divider value. When the
 * GPT is started counter will be decremented to 0. The rate at which this
 * count happens can be controlled by the prescaler divider value. GPT clock
 * is derived by dividing the CPU clock with the pre-scaler divider value.
 *
 * This test is having two parts. First part of the test verifies whether the
 * GTP is decrementing the counter or not. GPT is configured with a count value
 * 0xFFFF and pre-scaler divider value 256. GPT is started and counter value is
 * read. After few cycles of delay GPT counter value is read again. Both the
 * counter values are compared to verify whether the second count value is less
 * than the first counter value or not.
 *
 * During second part of the test timer count rate of the GPT is verified.
 * As the GPT clock is derived from the CPU clock based on the pre-scaler
 * value it possible to verify the GPT rate with respect to CPU clock rate.
 * GPT pre-scaler value is set to divide by 4. So the counter runs at a speed
 * that is 1/4th of the CPU clock. Clock at which the CPU is running during the
 * test is calculated using the function getSysClk(). This function returns
 * the value of system clock in KHz. Value of the system clock in KHz
 * represents the CPU clock cycles for one millisecond. GPT count value is set
 * to 1/4th of the CPU clock cycles for one millisecond. With this setup GPT
 * should take one millisecond to count down the counter value to 0. In other
 * way clock cycles executed by the CPU from the time GPT is started to the
 * time counter value reaches 0 should be equal to the number of cycles that
 * are executed by the CPU in one millisecond.GPT is configured to generate
 * interrupt when the count value reaches to 0. GPT is started and the CPU
 * clock cycles are counted in while loop. This loop increments a global
 * variable 'cpuCycleCount' until the GPT generate time-out interrupt.
 * This while loop execution is taking 12 CPU cycles. So the total CPU cycles
 * executed will be 12*cpuCycleCount. At the end of the test this CPU cycles
 * calculated are compared with the CPU clock cycles that will be executed in
 * one millisecond. The calculated CPU cycles can vary �1% from the actual
 * CPU cycles. If this condition is satisfied GPT is running at the configured
 * rate.
 *
 * NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5505 AND
 * C5515. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE
 * c55xx_csl\inc\csl_general.h.
 *
 * \subsection GPTy    TEST PROCEDURE:
 *  @li Open the CCS and connect the target (C5505/C5515 EVM)
 *  @li Open the project "CSL_GPTExampale_Out.pjt" and build it
 *  @li Load the program on to the target
 *  @li Set the PLL frequency to 12.288MHz
 *  @li Run the program and observe the test result
 *  @li Repeat the test at PLL frequencies 40, 60, 75 and 100MHz
 *  @li Repeat the test in Release mode
 *
 * \subsection GPTz    TEST RESULT:
 *  @li All the CSL APIs should return success
 *  @li Timer count value comparison should be successful in the first part of
 *      the test
 *  @li Timer should run at the configured rate in the second part of the test
 *
 *
 */

/* ============================================================================
 * Revision History
 * ================
 * 05-Oct-2008 Created
 * ============================================================================
 */

#include <stdio.h>
#include "csl_gpt.h"
#include "csl_intc.h"
#include <csl_general.h>
#include "ezdsp5535.h"
#include "ezdsp5535_led.h"

#define CSL_TEST_FAILED    (1u)
#define CSL_TEST_PASSED    (0)

#define CSL_PLL_DIV_000    (0)
#define CSL_PLL_DIV_001    (1u)
#define CSL_PLL_DIV_002    (2u)
#define CSL_PLL_DIV_003    (3u)
#define CSL_PLL_DIV_004    (4u)
#define CSL_PLL_DIV_005    (5u)
#define CSL_PLL_DIV_006    (6u)
#define CSL_PLL_DIV_007    (7u)

#define REG_TIAFR *(volatile ioport Uint16*) (0x1c14)

#define TIM_TIAFR_TIM0_FLAG    (0x0001u)
#define TIM_TIAFR_TIM1_FLAG    (0x0002u)

#define CSL_PLL_CLOCKIN    (32768u)

extern void VECSTART(void);
volatile Uint16    temp = 0;
volatile Uint16   count = 0;
volatile int i;
/**
 *  \brief  GPT Count Read Test function
 *
 * This is function verifies reading the counter values from the GPT
 *
 *  \param  none
 *
 *  \return CSL_TEST_PASSED  - Success
 *          CSL_TEST_FAILED  - Failure
 */
Int16 CSL_gptCountReadTest(void);

/**
 *  \brief  GPT Count Rate Verification test function
 *
 * This function verifies whether timer is running at the configured
 * rate or not. This function configures and enables the GPT interrupts
 * to indicate the expiry of the timer count. Test counts number of
 * cycles executed by the CPU after starting the timer till the expiry
 * of the timer. These cycles are used to verify the WDT count rate.
 * It is assumed that calculated CPU cycles will be with in the range
 * �1% actual CPU clock cycles. Test will be successful if the calculated
 * CPU cycles fall with in this range.
 *
 * NOTE: Changing the PLL setting in the middle (After getSysClk() call)
 *       of the test will result in test failure.
 *
 *  \param  none
 *
 *  \return CSL_TEST_PASSED  - Success
 *          CSL_TEST_FAILED  - Failure
 */
Int16 CSL_gptIntrTest(void);

/**
 *  \brief  Function to calculate the system clock
 *
 *  \param    none
 *
 *  \return   System clock value in KHz
 * 
 */
 
Int16 CSL_gpt0InteruptEvery100MicroSeconds(void);

/**
 *  \brief  Function to generate interupt at every 100us
 *
 *  \param    none
 *
 *  \return   System clock value in KHz
 * 
 */
 
Uint32 getSysClk(void);

/**
 *  \brief  GPT Interrupt Service Routine
 *
 *  \param  none
 *
 *  \return none
 */
interrupt void gptIsr(void);

/**
 *  \brief  main function
 *
 *  This function calls the GPT test function and displays the
 *  test result.
 *
 *  \param  none
 *
 *  \return none
 */
   /////INSTRUMENTATION FOR BATCH TESTING -- Part 1 --   
   /////  Define PaSs_StAtE variable for catching errors as program executes.
   /////  Define PaSs flag for holding final pass/fail result at program completion.
        volatile Int16 PaSs_StAtE = 0x0001; // Init to 1. Reset to 0 at any monitored execution error.
        volatile Int16 PaSs = 0x0000; // Init to 0.  Updated later with PaSs_StAtE when and if
   /////                                  program flow reaches expected exit point(s).
   /////
void main(void)
{
	Int16	result;
	Int16 i;
	EZDSP5535_LED_init( );  
		 
		
	CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_SP1MODE, MODE1);
	EZDSP5535_GPIO_init();
	
	EZDSP5535_LED_off( 1 ); // Turn on user LED i 
	EZDSP5535_LED_off( 3 );

		
	printf("CSL GPT TESTS!\n\n");
   /////INSTRUMENTATION FOR BATCH TESTING -- Part 3 -- 
   /////  At program exit, copy "PaSs_StAtE" into "PaSs".
        PaSs = PaSs_StAtE; //If flow gets here, override PaSs' initial 0 with 
   /////                   // pass/fail value determined during program execution.
   /////  Note:  Program should next exit to C$$EXIT and halt, where DSS, under
   /////   control of a host PC script, will read and record the PaSs' value.  
   /////
   result = CSL_gpt0InteruptEvery100MicroSeconds();
	if(CSL_TEST_FAILED == result)
	{
		printf("TIMER IS NOT GENERATING INTERUPT EVERY 100us!!\n");
   /////INSTRUMENTATION FOR BATCH TESTING -- Part 2 --   
   /////  Reseting PaSs_StAtE to 0 if error detected here.
        PaSs_StAtE = 0x0000; // Was intialized to 1 at declaration.
   /////
	}
	else
	{
		printf("TIMER IS NOT GENERATING INTERUPT EVERY 100us!!\n");
	}
   
   for(;;)
   {
   		EZDSP5535_LED_on( 3 );
   		for (i=0; i<10000;i++);
   		EZDSP5535_LED_off( 3 );
   		for (i=0; i<10000;i++);
   }
}

/**
 *  \brief  GPT Interupt generation function @100us
 *
 *  \param  none
 *
 *  \return CSL_TEST_PASSED  - Success
 *          CSL_TEST_FAILED  - Failure
 */
Int16 CSL_gpt0InteruptEvery100MicroSeconds(void)
{
	CSL_Handle    hGpt0;
	CSL_Handle    hGpt1;
	CSL_Status 	  status;
	CSL_Config 	  hwConfig0;
	CSL_Config 	  hwConfig1;
	CSL_GptObj	  gptObj0;
	CSL_GptObj	  gptObj1;
	CSL_TimRegsOvly regPtr0;
	CSL_TimRegsOvly regPtr1;

	status   = 0;

 /* Open the CSL GPT0 module */
	hGpt0 = GPT_open (GPT_0, &gptObj0, &status);
	if((NULL == hGpt0) || (CSL_SOK != status))
	{
		printf("GPT0 Open Failed\n");
		return (CSL_TEST_FAILED);
	}
	else
	{
		printf("GPT0 Open Successful\n");
	}

 /* Open the CSL GPT1 module */
	hGpt1 = GPT_open (GPT_1, &gptObj1, &status);
	if((NULL == hGpt1) || (CSL_SOK != status))
	{
		printf("GPT1 Open Failed\n");
		return (CSL_TEST_FAILED);
	}
	else
	{
		printf("GPT1 Open Successful\n");
	}

	/* Reset the GPT0 module */
	status = GPT_reset(hGpt0);
	if(CSL_SOK != status)
	{
		printf("GPT0 Reset Failed\n");
		return (CSL_TEST_FAILED);
	}
	else
	{
		printf("GPT0 Reset Successful\n");
	}
	
		/* Reset the GPT1 module */
	status = GPT_reset(hGpt1);
	if(CSL_SOK != status)
	{
		printf("GPT1 Reset Failed\n");
		return (CSL_TEST_FAILED);
	}
	else
	{
		printf("GPT1 Reset Successful\n");
	}
    
    /* Disable the CPU interrupts */
	IRQ_globalDisable();

	/* Clear any pending interrupts */
	IRQ_clearAll();

	/* Disable all the interrupts */
	IRQ_disableAll();
	
	IRQ_setVecs((Uint32)(&VECSTART));
	IRQ_plug(TINT_EVENT, &gptIsr);
	IRQ_enable(TINT_EVENT);

	hwConfig0.autoLoad 	 = GPT_AUTO_ENABLE;
	hwConfig0.ctrlTim 	 = GPT_TIMER_ENABLE;
	hwConfig0.preScaleDiv = GPT_PRE_SC_DIV_1;
	hwConfig0.prdLow 	 = 2500;  // timer count to generate interrupt every 100us
	hwConfig0.prdHigh 	 = 0x0000;

	/* Configure the GPT module */
	status =  GPT_config(hGpt0, &hwConfig0);
	if(CSL_SOK != status)
	{
		printf("GPT0 Config Failed\n");
		return (CSL_TEST_FAILED);
	}
	else
	{
		printf("GPT0 Config Successful\n");
	}
	
	hwConfig1.autoLoad 	 = GPT_AUTO_ENABLE;
	hwConfig1.ctrlTim 	 = GPT_TIMER_ENABLE;
	hwConfig1.preScaleDiv = GPT_PRE_SC_DIV_1;
	hwConfig1.prdLow 	 = 10000;  // timer count to generate interrupt every 100us
	hwConfig1.prdHigh 	 = 0x0000;

	/* Configure the GPT module */
	status =  GPT_config(hGpt1, &hwConfig1);
	if(CSL_SOK != status)
	{
		printf("GPT1 Config Failed\n");
		return (CSL_TEST_FAILED);
	}
	else
	{
		printf("GPT1 Config Successful\n");
	}
	/* Enable CPU Interrupts */
	IRQ_globalEnable();
	CSL_SYSCTRL_REGS->TIAFR = CSL_IAFR_TIMER_FLAG_0_1_2_RESETVAL;
	regPtr0 = hGpt0->regs;
	regPtr1 = hGpt1->regs;
	
	if ((regPtr0->TIMPRD1) == (regPtr1->TIMPRD1))
	printf("Both Timer period values are configured to same count\n");
	/* Start the Timers */
	GPT_start(hGpt0);
	GPT_start(hGpt1);

	/* Wait for the timer interrupt */
	return (CSL_TEST_PASSED);
	
}

interrupt void gptIsr(void)
{
	IRQ_clear(TINT_EVENT);
       temp = REG_TIAFR;
    if ( temp & TIM_TIAFR_TIM0_FLAG)
    {
    	/* Clear Timer Interrupt Aggregation Flag Register (TIAFR) */
    	REG_TIAFR |= TIM_TIAFR_TIM0_FLAG;
    	count++;
    }
    if (temp & TIM_TIAFR_TIM1_FLAG)
    {
    	/* Clear Timer Interrupt Aggregation Flag Register (TIAFR) */
    	REG_TIAFR |= TIM_TIAFR_TIM1_FLAG;
    	count =0;
    }

    EZDSP5535_LED_on(1);
    /* Enable CPU Interrupts */
	IRQ_globalEnable();
 }