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[C5535] Confirm the nRESET pin.

Guru 24520 points

Hi community member,

Please let me confirm the following two questions for Reset pin.

[Question.1]

Regarding to the datasheet, the RESET pin must be held low until all of the power supplies.

> The external reset signal on the RESET pin must be held low until all of the power supplies reach their operating voltage conditions.

Does the "all of the power supplies" mean "all power lines for C5535"??

[Question.2]

If yes, customer did not use the RESET pin during RTC-only mode.

Is my understanding correct?

If you have any question, please let me know.

Best regards.

Kaka 

  • Hi Kaka-san,

    Below are my answers:

    A1. With respect to device power supplies - The device includes four core voltage-level supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3 ), and four I/O supplies (DVDDIO, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3).

    A2. Following is details on Q2 (Reset in RTC only mode) :

    The RTC-only mode requires CVDDRTC, LDOI, and DVDDRTC  power domains to be powered. CVDDRTC must be powered using an external power source.

    For RTC only mode (Lowest power mode), the programmer can shut down the internal DSP_LDO, cutting power to the DSP core (CVDD) while an external supply provides power to the RTC (CVDDRTC and DVDDRTC). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core. When DSP_LDO comes out of reset, it is enabled to 1.3 V for the bootloader to operate. When the WAKEUP pin is asserted, the voltage on the DSP_LDOO pin will start ramping up and it is monitored by the internal POR. Until the voltage reaches to the threshold level, the internal POR will hold the internal POWERGOOD signal low, which provides solation to RTC during transition period. Once the voltage reaches to the threshold level, the internal POR asserts the internal POWERGOOD signal (logic level high) and it resets reset of the system and disables RTC isolation and enables CPU to communicate with RTC.

    During power down sequence in RTC only mode -  CPU must set the LDO_PD bit or the BG_PD bit in the RTCPMGT register. Once the LDO_PD bit or the BG_PD bit is set to 1, the DSP_LDOO will be internally shut off and it will cause the internal POR holds the internal POWERGOOD signal low, which creates isolation for RTC.

    Also, RTC has its own power-on-reset (POR) circuit which resets the registers in the RTC core domain when power is first applied to the CVDDRTC power pin. The RTC flops are not reset by the device's RESET pin nor the digital core's POR (powergood signal).

    Hope this clarifies.

    Regards

     Vasanth

     

  • Hi Vasanth,

    Thank you for you response.
    I understand that nRESET pin could not use for device reset during RTC-only mode.
    Because the RESET pin and the POWERGOOD signal are internally combined with logical AND gate to produce an hardware reset. So, the POWERGOOD is low during RTC only mode. And the power domain of nRESET pin is DVDDIO, shut down this power during RTC-only mode(Lowest power). This is why the nRESET pin could not use for device reset during RTC-only mode.

    Is my understanding correct? Just in case, I confirmed this behavior by using C5515EVM and the nRESET pin did not work during this mode.

    And please let me confirm the following question.
    1. Would you show us the release timing of nRESET pin when power on the device?
    If possbile, I would like to see the timing chart of power supply and release timing of nRESET pin.
    Regarding to your answer, they need to be held low until CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3, DVDDIO, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3 reach their operating voltage conditions. It seems that they must to be enabled the USB power domains in case of not using the USB function. And if use the some of other C553x family like C5532 or C5533 does not have USB functions. So, it seems that those devices cannot be satisfied with this limitation. 

    2. For USB power domain, those domains will be provided by USB_LDO. In my understanding, this LDO is disabled at RESET. So, if we would like to use this LDO, we need to control the resister on C5535.( I have asked this question on other thread.)  So, would you please clarify the enable timing of USB_LDO?

    3. I attached the power sequence timing of C55 device which I thought.  Would you please check whether there are any problem for those sequences(especially sheet 3(customer power on) and sheet4(customer RTC) )?

    1401.C5535 power sequence.xlsx

    ** I updated the attached file on 2015/8/27 18:44 JPN

    If you have any questions, please let me know.

    Best regards.
    Kaka

  • Hi Kaka-san,

    Below are my response ( with prefix VK)

    Because the RESET pin and the POWERGOOD signal are internally combined with logical AND gate to produce an hardware reset. So, the POWERGOOD is low during RTC only mode

    VK: This is correct

    The power domain of nRESET pin is DVDDIO, shut down this power during RTC-only mode(Lowest power). This is why the nRESET pin could not use for device reset during RTC-only mode.

    VK: I am not sure how the above was inferred. But in my understanding The hardware reset occurs whenever the RESET pin is asserted or when the internal power-on-reset (POR) circuit de-asserts an internal signal called POWERGOOD.

    While entering RTC only mode Once the LDO_PD bit or the BG_PD bit is set to 1, the DSP_LDOO will be internally shut off and it will cause the internal POR holds the internal POWERGOOD signal low (RESETn may be in de-asserted state). During the wakeup sequence the WAKEUP pin is asserted, the voltage on the DSP_LDOO pin will start ramping up and it is monitored by the internal POR. Until the voltage reaches to the threshold level, the internal POR will hold the internal POWERGOOD signal low, which provides isolation to RTC during transition period. Once the voltage reaches to the threshold level, the internal POR asserts the internal POWERGOOD signal (logic level high) and it resets reset of the system.

    Would you show us the release timing of nRESET pin when power on the device ?

     VK: Section 5.7.3.3 provides details on Reset Electrical Data and Timing.

    Regarding to your answer, they need to be held low until CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3, DVDDIO, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3 reach their operating voltage conditions. It seems that they must to be enabled the USB power domains in case of not using the USB function. And if use the some of other C553x family like C5532 or C5533 does not have USB functions. So, it seems that those devices cannot be satisfied with this limitation. 

     VK: As mentioned in the power up sequence If the USB subsystem is used, the subsystem must be powered up in the following sequence:

    • USB_VDDA1P3 and USB_VDD1P3
    • USB_VDDA3P3
    • USB_VBUS

    If the USB subsystem is not used, the following can be powered off:

    • USB Core - USB_VDD1P3, USB_VDDA1P3
    • USB PHY and I/O Level Supplies – USB_VDDOSC, USB_VDDA3P3, USB_VDDPLL

    With respect to C5532 The USB_LDOO is not supported on this device, so the USB_LDO must be left disabled. USB_LDO is disabled at reset, so it does not require any action to disable the USB_LDO. When the USB_LDO is disabled, the USB_LDOO pin is in a high-impedance (Hi- Z) state and must be left unconnected.

    For USB power domain, those domains will be provided by USB_LDO. In my understanding, this LDO is disabled at RESET. So, if we would like to use this LDO, we need to control the resister on C5535.( I have asked this question on other thread.)  So, would you please clarify the enable timing of USB_LDO?

    VK: Yes, at reset, the USB_LDO is turned off. The USB_LDO can be enabled via the USBLDOEN bit (bit 0) in the LDOCNTL register. The USB_LDO can be independently and dynamically enabled or disabled by software via the USB_LDO_EN bit in the LDOCNTL register.

     I attached the power sequence timing of C55 device which I thought.  Would you please check whether there are any problem for those sequences(especially sheet 3(customer power on) and sheet4(customer RTC) )?

     VK: Yes will review this and get back to you.

    Hope the above infromation Helps. 

    Regards

    Vasanth

  • Hi Vasanth,

    Thank you for your response.

    > VK: I am not sure how the above was inferred. But in my understanding The hardware reset occurs whenever the RESET pin is asserted or when the internal power-on-reset (POR) circuit de-asserts an internal signal called POWERGOOD.
    [Kaka]
    I could understand the above your comments. I had a misunderstanding.

    >Regarding to your answer, they need to be held low until CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3, DVDDIO, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3 reach their operating voltage conditions. It seems that they must to be enabled the USB power domains in case of not using the USB function. And if use the some of other C553x family like C5532 or C5533 does not have USB functions. So, it seems that those devices cannot be satisfied with this limitation.
    >VK: As mentioned in the power up sequence If the USB subsystem is used, the subsystem must be powered up in the following sequence:
    >USB_VDDA1P3 and USB_VDD1P3
    >USB_VDDA3P3
    >USB_VBUS
    >For USB power domain, those domains will be provided by USB_LDO. In my understanding, this LDO is disabled at RESET. So, if we would like to use this LDO, we need to control the resister on C5535.( I have asked this question on other thread.) So, would you please clarify the enable timing of USB_LDO?
    >VK: Yes, at reset, the USB_LDO is turned off. The USB_LDO can be enabled via the USBLDOEN bit (bit 0) in the LDOCNTL register. The USB_LDO can be independently and dynamically enabled or disabled by software via the USB_LDO_EN bit in the LDOCNTL register.

    [KAKA]
    Regarding to your comments as above, I am not cleared my concern.

    I know that the USB domain has power-up sequence and need to be satisfied with this.
    But the USB_LDO is not enabled at reset timing. And this LDO is controlled by register on C5535.
    In order to be enabled this LDO, we need to run the initialization program for this. It seems that this is impossible because the nRESET is held low until USB_VDDA1P3 or USB_VDD1P3 reach their operating voltage condition even though the USB_LDO is disabled.


    >Would you show us the release timing of nRESET pin when power on the device ?
    >VK: Section 5.7.3.3 provides details on Reset Electrical Data and Timing.
    [Kaka]
    I saw this figure, but I could not read the release timing of nRESET pin.
    Because The nRESET pin has already release in this figure even though the PWERGOOD is low.
    So it seems that this timing chart is not satisfied with the following note on datasheet.
    >> The external reset signal on the RESET pin must be held low until all of the power supplies reach their operating voltage conditions.


    >I attached the power sequence timing of C55 device which I thought. Would you please check whether there are any problem for those >sequences(especially sheet 3(customer power on) and sheet4(customer RTC) )?
    > VK: Yes will review this and get back to you.
    [Kaka]
    Thank you for your kindly corporation.
    I wait for your update.

    Best regards.
    Kaka

  • Hi Kaka-san,

    Below is my response.

    [Kaka] I saw this figure, but I could not read the release timing of nRESET pin.
    Because The nRESET pin has already release in this figure even though the PWERGOOD is low.
    So it seems that this timing chart is not satisfied with the following note on datasheet.
    >> The external reset signal on the RESET pin must be held low until all of the power supplies reach their operating voltage conditions.

    VK:  The figure is an illustration of reset and powergood combination. The RESET pin is combined with the internal POWERGOOD signal, that is generated by the MAIN POR, via an AND-gate. In the figure you could observe this too - look for "POWERGOOD (Internal) and RESET"

    The Main power-on reset (POR) circuit keeps the DSP in reset until specific voltages have reached predetermined levels. When the DSP_LDO is enabled externally by the DSP_LDO_EN pin, the output of the POR circuit, POWERGOOD, is held low until  -  LDOI is powered and the bandgap is active for at least approximately 8 ms,  - VDD_ANA is powered for at least approximately 4 ms, - DSP_LDOO is above a threshold of approximately 950 mV.

    When the DSP_LDO is disabled (DSP_LDO_EN pin = 1), the voltage monitoring on the DSP_LDOO pin is de-activated and the POWERGOOD signal is immediately set high. In this case, the RESET pin will be the sole source of hardware reset.

    So with respect to external reset signal, The reset needs to be held low until the respective voltages reaches the valid operating voltage condition, this along with the Main POR (powergood) will form the hardware reset.

    [KAKA] Regarding to your comments as above, I am not cleared my concern.

    I know that the USB domain has power-up sequence and need to be satisfied with this.
    But the USB_LDO is not enabled at reset timing. And this LDO is controlled by register on C5535.
    In order to be enabled this LDO, we need to run the initialization program for this. It seems that this is impossible because the nRESET is held low until USB_VDDA1P3 or USB_VDD1P3 reach their operating voltage condition even though the USB_LDO is disabled.

    VK: I understood what exactly you meant on this, I will get back to you .

    [KAKA] Attached the power sequence timing of C55 device.

    VK: Though it looks ok, but suggest you to wait until we comeback on USB LDO.

    Regards

     Vasanth

  • Hi Vasanth,

    Thank you for your confirming.

    >VK:  The figure is an illustration of reset and powergood combination. The RESET pin is combined with the internal POWERGOOD signal, that is generated by the MAIN POR, via an AND-gate. In the figure you could observe this too - look for "POWERGOOD (Internal) and RESET"

    [Kaka]

    Regarding to your comments, when the POWERGOOD(internal) is changed from Low to high, the DSP_LDOO reaches the valid operation voltage condition. So, the Figure on datasheet shows that the nRESET pin has already released even though the DPS_LDOO does not reach the valid operation voltage on power-up sequence.

    >So with respect to external reset signal, The reset needs to be held low until the respective voltages reaches the valid operating voltage condition, this along with the Main POR (powergood) will form the hardware reset.

    [Kaka]

    I do not understand why the nRESET pin must be held "Low" until all power domains reaches  the valid operating voltage condition.  The RESET pin  is combined with the internal POWERGOOD. The POWERGOOD signal is generated by DSP_LDOO(CVDD voltage). So, the CVDD reaches the valid voltage, the C5535 will happen the POR if  the nRESET pin has already released.  So would you please explain why nRESET pin must be held "Low" until all power domains reaches the valid operating voltage?

     

    > VK: Though it looks ok, but suggest you to wait until we comeback on USB LDO.

    [Kaka]

    OK. I am waiting your feedback about USB_LDO from you.

    Best regards.

    Kaka

  • Hi Kaka-san,

    My comments are below.

    [Kaka] - I do not understand why the nRESET pin must be held "Low" until all power domains reaches  the valid operating voltage condition.  The RESET pin  is combined with the internal POWERGOOD. The POWERGOOD signal is generated by DSP_LDOO(CVDD voltage). So, the CVDD reaches the valid voltage, the C5535 will happen the POR if  the nRESET pin has already released.  So would you please explain why nRESET pin must be held "Low" until all power domains reaches the valid operating voltage?

    VK. As for my understanding the reason for mentioning nRESET pin to be asserted until all the power supplies reach the valid voltage level is as follows: - Since there are many input supplies (not talking about LDOs here) to be applied to device, it would be difficult to characterize considering supplies at different level, so the option was to ensure input supplies are in valid operating voltage condition before releasing the nRESET pin.

    Also, when DSP_LDO is disabled (DSP_LDO_EN pin = 1), the voltage monitoring on the DSP_LDOO pin is de-activated and the POWERGOOD signal is immediately set high. In this case, the nRESET pin will be the sole source of hardware reset.

    With respect to the Figure (Figure 5-8) the caption seems to be confusing or incorrect. This is more applicable to RTC only mode scenario. The intention of these figures (figure5-8 & figure 5-9) is to demonstrate the conditions/status of various signal group, during device reset assertion and de-assertion.

    Hope this clarifies.

    Regards

     Vasanth

  • Hi Vasnth,

    Do you have any update for USB_LDO??

    Best regards.
    Kaka
  • Hi Kaka-san,

    It would take some more time (another week or so), its been reviewed internally. I will get back once I have data .

    Regards

     Vasanth

  • Hi Vasanth,

    Thank you for your kindly explanation for my question.
    Please let me confirm your comments.

    >Also, when DSP_LDO is disabled (DSP_LDO_EN pin = 1), the voltage monitoring on the DSP_LDOO pin is de-activated and the POWERGOOD signal is immediately set high. In this case, the nRESET pin will be the sole source of hardware reset.
    [Kaka]
    My customer use the internal LDOs including the DSP_LDO for their system. In this case, need we not satisfied with the nRESET pin limitation?

    >With respect to the Figure (Figure 5-8) the caption seems to be confusing or incorrect. This is more applicable to RTC only mode scenario.
    [Kaka]
    If the Figure5-8 is applicable to RTC-only mode, is there any problem to continue releasing the nRESET pin after Power-on the C5535?
    i.e. The nRESET pin status is "High" during the RTC-only mode. So, it need not to be held "Low" during the RTC-only mode.

    If you have any questions, please let me know.
    Best regards.
    Kaka
  • Hi Kaka-san,

    My customer use the internal LDOs including the DSP_LDO for their system. In this case, need we not satisfied with the nRESET pin limitation?

    VK : Still during initial power up it is recommended to takecare that  all supplies reach the valid voltage level before releasing the reset. As explained in my earlier post, since there are multiple power supplies that needs to be applied to device ithis is a suggested option. Though you use internal LDO and Internal powergood signal takes care of monitoring the threshold of DSP_LDO, its still recommended during initial power up you release reset once valid voltage is reached with all supplies.

    If the Figure5-8 is applicable to RTC-only mode, is there any problem to continue releasing the nRESET pin after Power-on the C5535?
    i.e. The nRESET pin status is "High" during the RTC-only mode. So, it need not to be held "Low" during the RTC-only mode.

    VK: Yes that's correct.

    Regards

     Vasanth
     

  • Hi Vasanth,

    Thank you for confirming my questions.
    I will inform the nRESET pin handling during RTC-only mode.

    Please provide your comment if you will be able to confirm the USB_LDO behavior at power-up and the means of "all power domains" in datasheet RESET pin notification. (i.e Confirm whether the all power domain is including the USB power domain or not. ) And please provide you comment for customer's power-up sequence by this confirming. Now customer trigger the power for DVDDIO or other 3.3V and nRESET line by USB_LDO.

    Best regards.
    Kaka
  • Hi Vasanth,

    I reported your information and currently situation to my customer.  They thought that it seem more likely that USB_LDO cannot use for trigger of 3.3V lines. So, customer think the other two power sequence designs. Would you please check whether there are any problem for this designs by end of this week in Japan time? Please check the document as below.

      C55_PowerBlock_20150902.pptx
    If you find any problem for them, please let me know.
    Best regards.
    Kaka

  • Hi Kaka-san,

    I have few questions, Attached file has my questions embedded in it ( look in Solution 2 slide ).

    Please clarify.

    Note:  We are not considering your proposed solution1.

    Also, with respect to nRESET in RTC only mode I would like to let you know that  - If customer is not considering this signal in RTC only mode this is fine, since its suggested to shutdown power to DVDDIO, this signal (nRESET) will not be valid in this mode.

    Regards

     Vasanth

    C55_PowerBlock_Questions.pptx

  • Hi Vasanth,

    We would like to consider our proposed solution No.1 because the system will increase in cost by adding the "switch". So would you please also provide your comment for solution No.1?

    And I answered your question on below pptx file. Please see it.

    C55_PowerBlock_answers.pptx

    >Also, with respect to nRESET in RTC only mode I would like to let you know that  - If customer is not considering this signal in RTC only mode this is fine, since its suggested to shutdown power to DVDDIO, this signal (nRESET) will not be valid in this mode.

    [Kaka]

    I apologize that I could not understand your comments. Does you mean that the nRESET pin should keep the "high" state during RTC-only mode? In my understanding, it is OK if this pin is "Low" state during RTC-only mode. Right?  If possible, would you please explain in other word?

    Best regards.

    Kaka

  • Hi Kaka-san, 

    Thanks for your answers,  now I am clear on Solution 2. 

    I have a question with solution-1 , how do you ensure USB 1.3V ( USB_VDD1P3 , USB_VDDA1P3 ) come up first and then USB 3.3 V (USB_VDDA3P3), from the solution-1 slide, this is not clear. Can you clarify, once clarified we will review this and get back to you. 

    Also with respect to nRESET pin: In RTC only mode since DVDDIO supply is off and nRESET pin is in DVDDIO domain(as mentioned by you earlier), so reset pin function doesn't matter (it can be high or low) in RTC only mode. Hope this clarifies. 

    Regards

     Vasanth

  • Hi Vasanth,

    I answered your question as below.

    >I have a question with solution-1 , how do you ensure USB 1.3V ( USB_VDD1P3 , USB_VDDA1P3 ) come up first and then USB 3.3 V (USB_VDDA3P3), from the solution-1 slide, this is not clear. Can you clarify, once clarified we will review this and get back to you.
    [Kaka]
    I summarized the USB domain power up sequence for solution No.1 as below.
    1. After power on the system, USB_VDD1P3 and USB_VDDA1P3 are powered by external 1.3V LDO.
    2. After enabled the ANA_LDO, the 3.1V line enabled by this LDO.
    3. Power supply the USB_VDDA3P3
    4. And release the nRESET pin
    5. Enable the VBUS power if it has connected the USB

    If you have any question, please let me know.

    Please let me confirm the your comment for reset pin just in case.
    The reset pin handling does not care during RTC only mode because the power domain of nRESET is DVDDIO which will be shutdown during this mode. Right?

    If you will reviewed them, please let me know whether those solutions are OK or not by end of next Friday(tomorrow) in U.S time.
    Best regards.
    Kaka

  • Hi Vasanth,

    Would you please your comments as soon as possible? We must answer this question to my customer by end of Wed in Japan time.
    Please provide your answers for my requests. I summarized them as below.
    1. Please comment for my question which is related to nRESET release timing as below.
    [Kaka]
    The USB domain has power-up sequence and need to be satisfied with this. But the USB_LDO is not enabled at reset timing. And this LDO is controlled by register on C5535. In order to be enabled this LDO, we need to run the initialization program for this. It seems that this is impossible because the nRESET is held low until USB_VDDA1P3 or USB_VDD1P3 reach their operating voltage condition even though the USB_LDO is disabled.

    2. Check whether there is any problem for their power-up sequence

    3. Please let me confirm the your comment for reset pin just in case.
    The reset pin handling does not care during RTC only mode because the power domain of nRESET is DVDDIO which will be shutdown during this mode. Right?

    I apologize for pushing again.
    Best regards.
    Kaka

  • Hi Kaka-san, 

    While reviewing below points came up. Could you please help answer this questions. 

    1. What threshold for 3.1V Enable?? untrimmed ANA_LDO will be applied to 3.1V enable. if threshold for 3.1V gate is too high (may never come out of reset with untrimmed ANA_LDO  voltage).
    2. Was recommended EN signal for 3.1V comes from DSP_LDO  instead of ANA_LDO – but makes little difference if always using DSP_LDO  and DSP_LDO_EN may be OFF

    Please clarify on the above 2.

    Withe respect to your question on nRESET, Yes your understanding is correct.

    Regards

     Vasanth

  • Hi Vasanth,

    Thank you for your reviewing. I answered your question in line as below.

    What threshold for 3.1V Enable?? untrimmed ANA_LDO will be applied to 3.1V enable. if threshold for 3.1V gate is too high (may never come out of reset with untrimmed ANA_LDO voltage).
    [Kaka]
    The minimum enabled threshold of 3.1V LDO is 1.0V. So, customer think that there is any problem for enabling this LDO because the ANA_LDO is 1.3V.

    Was recommended EN signal for 3.1V comes from DSP_LDO instead of ANA_LDO – but makes little difference if always using DSP_LDO and DSP_LDO_EN may be OFF
    [Kaka]
    If customer will use the DSP_LDO for enabling the 3.1V LDO, the output voltage will be 1.3V or 1.05V. The margin of enabling LDO is so small if the DSP_LDO is set 1.05V. This is why they will use the ANA_LDO for enabling 3.1V LDO.

    Does those answers clarify your question?
    Especially, I could not understand your question No.2.

    If you have any questions, please let me know.
    Best regards.
    Kaka

  • Hi Kaka-san, 

    The Minimum threshold expected is on the higher side (threshold of 3.1V LDO is 1.0V). Remember this will be the untrimmed voltage and is not guaranteed. 

    I need to check with the PE team and get back to you. 

    Regards

     Vasanth

  • Hi Vasanth
    Thank you for your kindly support.
    Would you please provide the schedule to answer for my questions?

    I need to inform the feedbacks to my customer as soon as possible.

    Best regards.
    Kaka
  • Hi Kaka-san,

    You mean the reply from PE team on the threshold values. I am trying to get it by this week.

    Please let me know if you had any other questions related to this.

    Regards

     Vasanth

  • Hi Vasanth,

    If you will get the feedback from PE team and clarify the your concern , can you answer for all my questions by this week?

    Best regards.
    Kaka

  • Hi Vasanth,

    >The Minimum threshold expected is on the higher side (threshold of 3.1V LDO is 1.0V). Remember this will be the untrimmed voltage and is not guaranteed.

    I apologized that I could not understand what you said. The ANA_LDOO voltage spec is defined by Datasheet as below.
    The minimum voltage is 1.24 voltage. So, there is not any problem to use it as enabling signal for 3.1V LDO.

    Best regards.
    Kaka

  • Hi Kaka-san,

    As per your power sequencing, the enable to the 3.1V is from ANA_LDO, and since reset in not released, the ANA_LDO output is untrimmed voltage.  The untrimmed ANA_LDO might be arround 950mV,  if enable(3.1 supply) threshold is higher, then it may never come out of reset with untrimmed ANA_LDO voltage.  Thats the reason I am trying to find the untrimmed voltage from the team here.

    Hope this clarifies.

    Also, Could you please start another E2E thread(post) for any questions you think unanswered. This way it would be easier to close.

    Regards

     Vasanth

  • Hi Vasanth,

    Thank you for your explanation.
    I could understand your concern. You will confirm whether the output ANA_LDO voltage is expected voltage(around 1.3V) while the C5535 reset status. Right?

    OK. I discuss only about Confirm the power-up sequence in this thread.
    I will re-post my following questions on other thread.
    1. Confirm the mean of "All power domain" in RESET release timing.
    2. Confirm whether there is any problem to power on the USB1.3V domain during RTC-only mode.

    Best regard.
    Kaka

  • Hi Kaka-san,

    Below is my response.

    You will confirm whether the output ANA_LDO voltage is expected voltage(around 1.3V) while the C5535 reset status. Right?

    VK:  Yes that's correct.

    I will re-post my following questions on other thread.
    1. Confirm the mean of "All power domain" in RESET release timing.
    2. Confirm whether there is any problem to power on the USB1.3V domain during RTC-only mode.

    VK: Thanks its easier to close this way, I have answered this in the other thread.

    Regards

     Vasanth

     

  • Hi Kaka-san,

    I got inputs on the untrimmed ANA_LDO, the untrimmed ANA_LDO  voltage is arround 1V , looks this meets the expected threshold of 1V.

    Hope this clarifies.

    Regards

     Vasanth

  • Hi Vasanth,

    Thank you for your confirming.
    So, customer can use the both solution No.1 and No.2 for their system.  Right?


    Best regards.
    Kaka

  • Hi Kaka-san,

    Yes, ensure the usb power sequencing is followed ( USB 1.3V to come up first and then USB 3.3V ) and one more recommendation from the review is that reset superviser circuit have built in delay to allow all rails to stabilize (some amount of ms).

    Hope this clarifies.

    Regards

     Vasanth

  • Hi Vasanth,

    Thank you for your response.
    I will inform that the power sequence is looks like ok and recommend to add the supervisor circuit.

    Best regards.
    Kaka
  • Hi Vasanth,

    Could you please define the minimum voltage of ANA_LDO in RESET states?
    Can we think that the ANA_LDO voltage must not be below 1V on any status of C5535 except removing the LDOI and RTC-only mode?

    We requested us to provide the minimum voltage of ANA_LDO while C5535 RESET status.

    Best regards.
    Kaka

  • Hi Kaka-san,

     With respect to ANA_LDO this is answered in another thread raised by you. Refer to the below link.

     

    Regards

     Vasanth