Hello,
We are having a problem at times with SPI on C5505 with multiple slaves. We have been using the part for some time with a serial flash, LCD display, and MicGain POT being the 3 devices (CS0, CS1, CS2). I have added a flash-resident fonts feature that involves switching quickly between flash and LCD, and of course reconfiguring the SPI peripheral when necessary to switch the chip select, etc. There have been serial flash read errors at times. What I see is the flash transaction generating 5 clocks rather than the 8 that we require. What I see just ahead of the flash command that fails is a brief (about 10ns) blip where both the flash (CS0) and LCD (CS1) are selected - active low. There is no SPI bus activity at that time - it occurs with the flash read. Other flash commands succeed once the SPI_config is re-executed.
One thing I notice is that after the failed flash read occurs, the SPICDR register is set to 0000 (it normally is 5). System clock is 120MHz so this is a divide by 6 to get 20MHz as SPI clock frequency for the serial flash (same rate on LCD).
We are using the v3.03 CSL plus some routines I added to claim the SPI (config if device is different, otherwise allows more transactions).
Do you have any idea what is causing this? This is very urgent so please let me know if you have an explanation or solution.
Thanks.
Stephen Thruston
