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[C5535] Confirm the SAR function

Kaka
Guru 24520 points

Hi TI Experts,

I have already asked the similar questions related to the SAR on other threads.

Please let me confirm the following question in addition to this.
[Question.1]
Would you please teach the means of "Vt" at the formula of "VDD_ANA-Vt" on Figure 11-1. SAR Converter?

[Question.2]
How much is the maximum "VDD_ANA - Vt" voltage in consideration of the variation?

[Question.3]
According to the datasheet of C5535 on page 35, the GPAIN0 pin is unable to accept signals greater than VDDA_ANA without clamping. But I think that the GPAIN0 pin is unable to accept signal greater than "VDD_ANA - Vt" without clamping. Is my understanding correct?
If yes, would you please revise the datasheet?
If no, would you please show us the method to input the GPAIN0 to the maximum voltage up to the VDD_ANA without clamping?

If you have any questions, please let me know.
Best regards.
Kaka

Kaka

  • 0
    TI__Genius 12575 points

    Hi Kaka-san,

     The SAR related questions that you had asked has been answered in the other thread.

     

     Please let us know if you have additional questions.

    Regards

     Vasanth

     

  • 0 in reply to Vasantha K
    Guru 24520 points

    Hi Vasanth,

    I checked your answers but I could not be clear my concerns.
    Please provide us the following questions(this is the same on the other thread)

    Q1. According to the TRM, the NoVH must be "1" to measure ch2.
    So, if we would like to use the CH2, we need to disable the NoVH.
    And according to the following E2E thread, the NoVH control bit is bit 2(Reversed bit) on SARPINCTRL.
    e2e.ti.com/.../326102
    >[Q]
    >I have confirmed that the conversion fails if bit 2 is not set despite the fact that bit 2 is "reserved" according to table 11-6 in the technical >reference manual. Is this behavior documented somewhere?
    >[ANS]
    >This is to disable the high voltage protection circuits which prevent conversion when the analog voltage (AVdd) is lower than the voltage at >the GPAIN0 pin; and the maximum allowed voltage at the GPAIN0 pin is 3.6V. Can you check the voltages you have?

    Is my understanding correct?

    Q2. If disabled the NoVH feature, will be the channel 2 disabled when the input voltage is bigger than VDDA_ANA?

    Q3. If we set the bit 2(Control NoVH Enable/Disable) on SARPINCRT, is there any problem to read the value of CH3?
    Customer would like to use the same register value of SARPINCTRL when read the CH3.

    Q4. Would you please teach the means of "Vt" at the formula of "VDD_ANA-Vt" on Figure 11-1. SAR Converter?

    Q5. How much is the maximum "VDD_ANA - Vt" voltage in consideration of the variation when the NoVH is disabled?

    Q6.According to the datasheet of C5535 on page 35, the GPAIN0 pin is unable to accept signals greater than VDDA_ANA without clamping. But I think that the GPAIN0 pin is unable to accept signal greater than "VDD_ANA - Vt" without clamping when NoVH is disabled.
    Is my understanding correct?

    If yes, would you please revise the datasheet?
    If no, would you please show us the method to input the GPAIN0 to the maximum voltage up to the VDD_ANA without clamping?

    Best regards.
    Kaka

  • 0 in reply to Kaka
    TI__Genius 12575 points

    Hi Kaka-san,

    I understand your questions thanks for clarifying. We are reviewing NoHV feature internally and will get back with the details soon. I will also answer all your other related questions once its concluded.

    Regards

     Vasanth

  • 0 in reply to Vasantha K
    Guru 24520 points
    Hi Vasanth,

    Thank you for your kindly supports. I am waiting for your kindly feedback.

    Best regards.
    Kaka
  • 0 in reply to Kaka
    Guru 24520 points
    Hi Vasanth,

    Any update on this?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Genius 12575 points
    Hi Kaka-san,

    This would take few more days. Will get back once I have an update on this.

    Regards
    Vasanth
  • 0 in reply to Vasantha K
    Guru 24520 points
    Hi Vasanth,

    Thank you for explain your status.
    I will waiting for your kindly feedback.

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Genius 12575 points

    Hi kaka-san,

    Below are the response (Marked A1 to A6) for your Questions.

    Q1.  According to the TRM, the NoVH must be "1" to measure ch2.  So, if we would like to use the CH2, we need to disable the NoVH.  And according to the following E2E thread, the NoVH control bit is bit 2(Reversed bit) on SARPINCTRL.  e2e.ti.com/.../326102
    >[Q]  I have confirmed that the conversion fails if bit 2 is not set despite the fact that bit 2 is "reserved" according to table 11-6 in the technical >reference manual. Is this behavior documented somewhere?
     >[ANS] This is to disable the high voltage protection circuits which prevent conversion when the analog voltage (AVdd) is lower than the voltage at >the GPAIN0 pin; and the maximum allowed voltage at the GPAIN0 pin is 3.6V. Can you check the voltages you have?

     

    A1:  If you use Channel 2, I see couple of issues :

     

    1 If you set NoVH then, the voltage gets clamped at (VDD_ANA / 2) which is equal to ~0.65V

    2. If you do not set NoHV then again here the voltage gets clamped at (Vdd_ANA – Vt).

     

    So its recommended to use other channels instead of Channel2.


      
    Q2. If disabled the NoVH feature, will be the channel 2 disabled when the input voltage is bigger than VDDA_ANA?

     

    A2:  Yes, whenever its bigger than (VDD_ANA – vt).


    Q3. If we set the bit 2(Control NoVH Enable/Disable) on SARPINCRT, is there any problem to read the value of CH3?
    Customer would like to use the same register value of SARPINCTRL when read the CH3.

     

    A3: No. It’s not possible to select multiple channel at a time. Channel 3 is isolated from Channel0.


    Q4. Would you please teach the means of "Vt" at the formula of "VDD_ANA-Vt" on Figure 11-1. SAR Converter?

     

     A4:  vt – is threshold voltage for NMOS transistor. It’s not a datasheet parameter, but it could be as high as 700mV.

    Q5. How much is the maximum "VDD_ANA - Vt" voltage in consideration of the variation when the NoVH is disabled?

     

     A5: This depends on the threshold voltage of NMOS transistor, which is answered in Q4.


    Q6.According to the datasheet of C5535 on page 35, the GPAIN0 pin is unable to accept signals greater than VDDA_ANA without clamping. But I think that the GPAIN0 pin is unable to accept signal greater than "VDD_ANA - Vt" without clamping when NoVH is disabled.
    Is my understanding correct?

     

    A6: Yes that’s correct. This is noted for further actions.

     

    Please let me know if you have additional questions.

     

    Regards

    Vasanth

  • 0 in reply to Vasantha K
    Guru 24520 points
    Hi Vasanth,

    Thank you for your updates. I will be able to answer for almost customer's questions.
    For Q3, please let me re-confirm this.

    If we set the bit 2(Control NoVH Enable/Disable) on SARPINCRT, is there any problem to read the value of CH3 by set the CHSEL register as AIN3(011b)?
    Customer would like to use the same register value of SARPINCTRL when read the CH3. And they would not select and read the CH2 and CH3 at the same time. i.e : SAR register will be set as below.
    SRACRL: 0xB000
    SRAINCTRL: 0x3104
    How do you think?
    In my EVM, it seems that C5535 can read the CH3 values without any problem at the above settings.

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Genius 12575 points

    Hi Kaka-san,

    As mentioned in my earlier response - Channel 3 is isolated from other channels. So it looks ok to me.

    Regards

     Vasanth

  • 0 in reply to Vasantha K
    Guru 24520 points
    Hi Vasanth,

    Thank you for your response.
    If I will get more questions from customer, please let me confirm them.
    Best regards.
    Kaka