Ezdsp5535, PLL never start realy ??

bouille julien

Hi, i can't make the pll start correctly.

I try mesure it with the audio interrupt that appen @ 48khz and using the clock counting tools in CCS
But i can't get more than 90 clock count on each interrupt wich mean that i m running @ 12mHZ

Ive try to put the SW3 pin1 on the dual position but without succes.
Here is the return i have from consol:

PLL frequency 100 MHz
REGISTER --- CONFIG VALUES
PLL_CNTRL1   82fa --- 82fa
PLL_CNTRL2   080e --- 0806 Test Lock Mon will get set after PLL is up
PLL_CNTRL3   8000 --- 8000
PLL_CNTRL4   0000 --- 0000

Any feedback would be much appreciate

Regards.

over 8 years ago

0 Vasantha K over 8 years ago

TI__Genius 12575 points

Hi,

Can you try with the below mentioned PLL configuration.

CGCR1 = 0x8BE8;
CGCR2 = 0x8000;
CGCR3 = 0x0806;
CGCR4 = 0x0000;

Regards

Vasanth

0 bouille julien over 8 years ago in reply to Vasantha K

Prodigy 215 points

Can you give me a simple C code to init the PLL ?
because i use a obsure C++ function for now, and i dont realy know what appen behin it.

0 bouille julien over 8 years ago

Prodigy 215 points

i ve tried you setting but i run at alf speed compared to befor.
I now count 45 clock between each 48khz interrupts.
Wich make me think i run @ 48000*45 = +- 1.3MHZ :(

0 Vasantha K over 8 years ago in reply to bouille julien

TI__Genius 12575 points

Can you check clock out pin (TP4) and confirm the frequency ? While checking , ensure you have correct configuration in CLKOUT Control Source Select Register (CCSSR).

Regards
Vasanth

0 bouille julien over 8 years ago in reply to Vasantha K

Prodigy 215 points

here is the begin of my new code:
void main( void )
{

/* Initialize BSL */
USBSTK5505_init( );

/* Initialize PLL */

printf("PLL SETUP BEGIN! \n");
CLK_CGCR1 = 0x0000; //SET CLR CNTL TO 0
CLK_CGCR2 = 0x0000; //SET CLR CNTL TO 0

CLK_CLKSTOP = CLK_CLKSTOP & 0xFFCF;

SYS_EXBUSSEL = 0x1000;

/* CGCR1 - Section 1.4.4.1 */
/* PLL power up. PLL Multiplier M = 1000 */
CLK_CGCR1 = 0x81c8; //PG1.4: 0x82FA;
/* CGCR2 - Section 1.4.4.2 */
CLK_CGCR2 = 0x8000; /* Bypass reference divider */
/* CGCR3 - Section 1.4.4.3 */
CLK_CGCR3 = 0x0806; /* initialization bits */
/* CGCR4 - Section 1.4.4.4 */
CLK_CGCR4 = 0x0000; /* Bypass output divider */

// Peripheral Reset
SYS_PRCNTR = 0x0008; // Software reset signals asserted after 2clock cycles
SYS_PRCNTRLR = 0x00FF; // Reset all peripherals.

for (i=0; i< 0xFFFF; i++); // Wait in for loop to give time for peripherals to reset.
for (i=0; i< 0xFFFF; i++); // Wait in for loop to give time for peripherals to reset.
//---------- PLL SETUP END -------------
printf("PLL SETUP END \n");
printf("REGISTER --- CONFIG VALUES\n");
printf("PLL_CGCR1 --- 0x%X \n", CLK_CGCR1);
printf("PLL_CGCR2 --- 0x%X \n", CLK_CGCR2);
printf("PLL_CGCR3 --- 0x%X \n", CLK_CGCR3);
printf("PLL_CGCR4 --- 0x%X \n", CLK_CGCR4);
printf("PLL_CCR2 --- 0x%X \n", CLK_CCR2);

0 bouille julien over 8 years ago in reply to Vasantha K

Prodigy 215 points

and the maped memory reg

#define CLK_CGCR1 *(volatile ioport Uint16*)(0x1c20)
#define CLK_CGCR2 *(volatile ioport Uint16*)(0x1c21)
#define CLK_CGCR3 *(volatile ioport Uint16*)(0x1c22)
#define CLK_CGCR4 *(volatile ioport Uint16*)(0x1c23)
#define CLK_CCR2 *(volatile ioport Uint16*)(0x1c1f)

#define CLK_CCSSR *(volatile ioport Uint16*)(0x1C24)
#define CLK_CLKSTOP *(volatile ioport Uint16*)(0x1C3A)

will mesure the test point with my oscilloscope...

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Ezdsp5535, PLL never start realy ??