• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 102 subscribers
  • Views 1961 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

The source code of ASRC on C55 connected audio framework

user1895036
Prodigy 250 points

Can I get the source code of ASRC(sample rate converter) on C55 connected audio framework.

The library of ASRC (asrc_dly_fix_lib.lib） on current "connected audio framework" is build for C55x CPU Rev 3.x.

But I want to use this framework with other libraries built for CPU Re v2.X.

Now I got an error :

asrc_dly_fix_lib.lib<asrc_dly_fix.ob
j>" specifies "C55x CPU Rev 3.x", which is not compatible with "C55x CPU Rev
2.x" specified in a previous file or on the command line

So I want to build ASRC library build for CPU Rev 2.0.

  • 0
    TI__Genius 12575 points

    Hi,

    We are looking at this and will get back to you.

    Regards

     Vasanth

  • 0
    TI__Mastermind 29180 points

    Hello,

    We are looking into providing access to the ASRC source code - its currently on an internal GIT repo. Maybe I can simply provide a lib file built for CPU rev 2.0 if that is what you need.

    But I question what C55xx device you are building code for. See this wiki and mapping of CPU revisions to devices: C55x_CPU_revision.pdf

    http://processors.wiki.ti.com/index.php/C55x_Common_Errors_and_Fixes#Fatal_Error:_.3Csome_file.3E_specifies_.22C55x_CPU_Rev_3.x.22.2C_which_is_not_compatible_with_.22C55x_CPU_Rev_2.x.22

    If you are building for C5504/5, C5514/5, C5532/3/4/5, C5545, then the CPU revision should be 3.3 and you should attempt to rebuild your other libraries to match. Is that possible?

    I believe these processors can execute code built with older CPU revisions, but wont be optimized to use the new architecture features added to CPU Rev 3.3.

    Search the term "revision" in the C55x v3.x CPU Reference Guide: http://www.ti.com/lit/ug/swpu073e/swpu073e.pdf

    Hope this helps,
    Mark

  • 0 in reply to Mark Mckeown
    TI__Mastermind 29180 points

    I rebuilt the asrc_dly_fix_lib.lib library for cpu2.0 [edited] (small and large memory models). See attached:

    /cfs-file/__key/communityserver-discussions-components-files/791/6567.asrc_5F00_dly_5F00_fix_5F00_lib_5F00_cpu2.0.zip

    As a sanity check, I also rebuilt for cpu3.3 and compared the unarchiver output (ar55.exe) but I got slightly different file sizes, but close...

    Huge memory model not supported for cpu revisions 1 or 2

    See attached lib files, below unarchiver comparisons of the .lib files I built againt the original lib file, and the console remarks regarding instructions that might not run correctly with cpu:2.0 setting.

    I used CGT 4.3.8, just like the original lib file was built with: http://software-dl.ti.com/codegen/non-esd/downloads/download.htm

    =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-

    =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-

    Unarchiver outputs...

    C5500 Code Generation Tools 4.3.8 (release, small mem model, cpu:3.3)

    C:\CCS_6.1.3.00033\ccsv6\tools\compiler\c5500_4.4.1\bin>ar55 -tv C:\test_asrc_li

    b\asrc_dly_fix_lib.lib

         SIZE   DATE                        FILE NAME

     --------   ------------------------    -----------------

        12562   Tue Feb 07 10:11:35 2012    asrc_dly_fix.obj

         1944   Wed Jan 25 16:01:19 2012    firPPF_ASRC_mono_bilin_decby2.obj

         2138   Wed Jan 25 16:01:21 2012    firPPF_ASRC_stereo_bilin_decby2.obj

    =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-

    Compiler version TI v4.3.8 (release, small mem model, cpu:3.3)

    C:\CCS_6.1.3.00033\ccsv6\tools\compiler\c5500_4.4.1\bin>ar55 -tv C:\test_asrc_li

    b\asrc_dly_fix_lib_small_mem_cpu3.3_cgt4.3.8_release.lib

         SIZE   DATE                        FILE NAME

     --------   ------------------------    -----------------

        12617   Thu Jun 16 13:36:24 2016    asrc_dly_fix.obj

         1938   Thu Jun 16 13:36:25 2016    firPPF_ASRC_mono_bilin_decby2.obj

         2131   Thu Jun 16 13:36:26 2016    firPPF_ASRC_stereo_bilin_decby2.obj

    C:\CCS_6.1.3.00033\ccsv6\tools\compiler\c5500_4.4.1\bin>

    =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-

    Compiler version TI v4.3.8 (release, small mem model, cpu:2.0)

    C:\CCS_6.1.3.00033\ccsv6\tools\compiler\c5500_4.4.1\bin>ar55 -tv C:\test_asrc_li

    b\asrc_dly_fix_lib_small_mem_cpu2.0_cgt4.3.8_release.lib

         SIZE   DATE                        FILE NAME

     --------   ------------------------    -----------------

        12620   Thu Jun 16 13:38:31 2016    asrc_dly_fix.obj

         1938   Thu Jun 16 13:38:32 2016    firPPF_ASRC_mono_bilin_decby2.obj

         2131   Thu Jun 16 13:38:33 2016    firPPF_ASRC_stereo_bilin_decby2.obj

    C:\CCS_6.1.3.00033\ccsv6\tools\compiler\c5500_4.4.1\bin>

    =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-

    =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-

    See below build remarks / warnings (due to cpu revision 2.0)...

    **** Build of configuration Release for project c55_asrc_ccs6 ****

    "C:\\CCS_6.1.3.00033\\ccsv6\\utils\\bin\\gmake" -k all

    'Building file: ../asrc_dly_fix.c'

    'Invoking: C5500 Compiler'

    "C:/CCS_6.1.3.00033/ccsv6/tools/compiler/c5500_4.3.8/bin/cl55" -vcpu:2.0 -O2 --define=c5515 --include_path="C:/CCS_6.1.3.00033/ccsv6/tools/compiler/c5500_4.3.8/include" --include_path="C:/c55_lp/c55_asrc-c55_asrc/C55x_code/algorithm/inc" --display_error_number --diag_warning=225 --ptrdiff_size=16 --memory_model=small --preproc_with_compile --preproc_dependency="asrc_dly_fix.d"  "../asrc_dly_fix.c"

    "../asrc_dly_fix.c", line 134: warning #225-D: function declared implicitly

    "../asrc_dly_fix.c", line 204: warning #179-D: variable "polyphaseFiltPhase" was declared but never referenced

    "../asrc_dly_fix.c", line 210: warning #179-D: variable "coefIdx" was declared but never referenced

    "../asrc_dly_fix.c", line 210: warning #179-D: variable "dataIdx" was declared but never referenced

    "../asrc_dly_fix.c", line 211: warning #179-D: variable "sampCtr" was declared but never referenced

    "../asrc_dly_fix.c", line 212: warning #179-D: variable "tap" was declared but never referenced

    "../asrc_dly_fix.c", line 213: warning #179-D: variable "accL" was declared but never referenced

    "../asrc_dly_fix.c", line 213: warning #179-D: variable "accR" was declared but never referenced

    "../asrc_dly_fix.c", line 215: warning #179-D: variable "phase" was declared but never referenced

    "../asrc_dly_fix.c", line 216: warning #179-D: variable "accL2" was declared but never referenced

    "../asrc_dly_fix.c", line 216: warning #179-D: variable "accR2" was declared but never referenced

    "../asrc_dly_fix.c", line 217: warning #179-D: variable "y2" was declared but never referenced

    "../asrc_dly_fix.c", line 217: warning #179-D: variable "yout" was declared but never referenced

    "../asrc_dly_fix.c", line 218: warning #179-D: variable "y1" was declared but never referenced

    "../asrc_dly_fix.c", line 218: warning #179-D: variable "round_factor" was declared but never referenced

    "../asrc_dly_fix.c", line 221: warning #179-D: variable "cirBuf_idx_rd" was declared but never referenced

    "../asrc_dly_fix.c", line 223: warning #179-D: variable "decby2_loop_cnt" was declared but never referenced

    "../asrc_dly_fix.c", line 938: warning #225-D: function declared implicitly

    'Finished building: ../asrc_dly_fix.c'

    ' '

    'Building file: ../firPPF_ASRC_mono_bilin_decby2.asm'

    'Invoking: C5500 Compiler'

    "C:/CCS_6.1.3.00033/ccsv6/tools/compiler/c5500_4.3.8/bin/cl55" -vcpu:2.0 -O2 --define=c5515 --include_path="C:/CCS_6.1.3.00033/ccsv6/tools/compiler/c5500_4.3.8/include" --include_path="C:/c55_lp/c55_asrc-c55_asrc/C55x_code/algorithm/inc" --display_error_number --diag_warning=225 --ptrdiff_size=16 --memory_model=small --preproc_with_compile --preproc_dependency="firPPF_ASRC_mono_bilin_decby2.d"  "../firPPF_ASRC_mono_bilin_decby2.asm"

    "..\firPPF_ASRC_mono_bilin_decby2.asm", REMARK   at line 283: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

    SFTS   AC3,#10,AC3            

    "..\firPPF_ASRC_mono_bilin_decby2.asm", REMARK   at line 368: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

    MOV  AC3<<T1,*SP(#NPHASES_OFF) ; store Nphases in stack

    "..\firPPF_ASRC_mono_bilin_decby2.asm", REMARK   at line 396: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

       SFTS    AC0,T1,AC3                         ; AC3 = AC0<<T1                    

    "..\firPPF_ASRC_mono_bilin_decby2.asm", REMARK   at line 446: [R5505]

            This instruction will not behave correctly when it follows the MMR

              read of SP/SSP on line 445 and interrupts are enabled. Ensure at

              least 2 cycles occur between these two instructions. (see the C55x

              silicon exceptions errata; Advisory cpu_84)

    XCC    AC3==#0

    "..\firPPF_ASRC_mono_bilin_decby2.asm", REMARK   at line 448: [R5505]

            This instruction will not behave correctly when it follows the MMR

              read of SP/SSP on line 447 and interrupts are enabled. Ensure at

              least 2 cycles occur between these two instructions. (see the C55x

              silicon exceptions errata; Advisory cpu_84)

    XCC    AC3!=#0                             ; IF AC3!=0 execute next statement

    "..\firPPF_ASRC_mono_bilin_decby2.asm", REMARK   at line 450: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

    SFTS   AC3,#16,AC3                         ; AC3 = AC3<<16

    "..\firPPF_ASRC_mono_bilin_decby2.asm", REMARK   at line 478: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

    SFTS    AC2,#16,AC2                        ; AC2 = AC2<<16

    "..\firPPF_ASRC_mono_bilin_decby2.asm", REMARK   at line 485: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

       SFTS    AC3,11,AC3                         ; AC3 = AC3<<DELTA_NBITS (phase*yout_delta+yout1)<<DELTA_NBITS

    "..\firPPF_ASRC_mono_bilin_decby2.asm", REMARK   at line 490: [R5505]

            This instruction will not behave correctly when it follows the MMR

              read of SP/SSP on line 489 and interrupts are enabled. Ensure at

              least 2 cycles occur between these two instructions. (see the C55x

              silicon exceptions errata; Advisory cpu_84)

    XCC     AC3<#0                             ; if AC3<0 execute next instruction

    "..\firPPF_ASRC_mono_bilin_decby2.asm", REMARK   at line 544: [R5503]

            This instruction will not behave correctly when it follows the MMR

              write of SP/SSP on line 535 and interrupts are enabled. Ensure at

              least 4 cycles occur between these two instructions. (see the C55x

              silicon exceptions errata; Advisory cpu_84)

    XCC     AC3>=#0                         ; if AC3>0 execute next instruction

    "..\firPPF_ASRC_mono_bilin_decby2.asm", REMARK   at line 544: [R5505]

            This instruction will not behave correctly when it follows the MMR

              read of SP/SSP on line 543 and interrupts are enabled. Ensure at

              least 2 cycles occur between these two instructions. (see the C55x

              silicon exceptions errata; Advisory cpu_84)

    XCC     AC3>=#0                         ; if AC3>0 execute next instruction

    'Finished building: ../firPPF_ASRC_mono_bilin_decby2.asm'

    ' '

    'Building file: ../firPPF_ASRC_stereo_bilin_decby2.asm'

    'Invoking: C5500 Compiler'

    "C:/CCS_6.1.3.00033/ccsv6/tools/compiler/c5500_4.3.8/bin/cl55" -vcpu:2.0 -O2 --define=c5515 --include_path="C:/CCS_6.1.3.00033/ccsv6/tools/compiler/c5500_4.3.8/include" --include_path="C:/c55_lp/c55_asrc-c55_asrc/C55x_code/algorithm/inc" --display_error_number --diag_warning=225 --ptrdiff_size=16 --memory_model=small --preproc_with_compile --preproc_dependency="firPPF_ASRC_stereo_bilin_decby2.d"  "../firPPF_ASRC_stereo_bilin_decby2.asm"

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 346: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

    SFTS   AC3,#10,AC3                         ; AC3 = AC3<<10

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 439: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

    MOV  AC3<<T1,*SP(#NPHASES_OFF) ; store Nphases in stack

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 468: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

       SFTS    AC0,T1,AC3                        ; AC3 = AC0<<T1                    

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 535: [R5505]

            This instruction will not behave correctly when it follows the MMR

              read of SP/SSP on line 534 and interrupts are enabled. Ensure at

              least 2 cycles occur between these two instructions. (see the C55x

              silicon exceptions errata; Advisory cpu_84)

    XCC    AC3==#0

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 537: [R5505]

            This instruction will not behave correctly when it follows the MMR

              read of SP/SSP on line 536 and interrupts are enabled. Ensure at

              least 2 cycles occur between these two instructions. (see the C55x

              silicon exceptions errata; Advisory cpu_84)

    XCC    AC3!=#0                  ; IF AC3!=0 execute next statement

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 539: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

    SFTS   AC3,#16,AC3              ; AC3 = AC3<<16

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 574: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

    SFTS    AC2,#16,AC2                 ; AC2 = AC2<<16

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 581: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

       SFTS    AC3,11,AC3                  ; AC3 = AC3<<DELTA_NBITS (phase*yout_delta+y1L)<<DELTA_NBITS

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 586: [R5505]

            This instruction will not behave correctly when it follows the MMR

              read of SP/SSP on line 585 and interrupts are enabled. Ensure at

              least 2 cycles occur between these two instructions. (see the C55x

              silicon exceptions errata; Advisory cpu_84)

    XCC     AC3<#0                      ; if AC3<0 execute next instruction

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 599: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

    SFTS    AC2,#16,AC2                 ; AC2 = AC2<<16

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 606: [R5673]

            If accumulator shift left operation overflows, M40 == 0, SXMD == 0,

              and C54CM == 0, then the shift operation may not yield the

              appropriate saturated result; (see the C55x silicon exceptions

              errata; Advisory cpu_89)

       SFTS    AC3,11,AC3                  ; AC3 = AC3<<DELTA_NBITS (phase*yout_delta+y1R)<<DELTA_NBITS

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 611: [R5505]

            This instruction will not behave correctly when it follows the MMR

              read of SP/SSP on line 610 and interrupts are enabled. Ensure at

              least 2 cycles occur between these two instructions. (see the C55x

              silicon exceptions errata; Advisory cpu_84)

    XCC     AC3<#0                      ; if AC3<0 execute next instruction

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 691: [R5503]

            This instruction will not behave correctly when it follows the MMR

              write of SP/SSP on line 682 and interrupts are enabled. Ensure at

              least 4 cycles occur between these two instructions. (see the C55x

              silicon exceptions errata; Advisory cpu_84)

    XCC     AC3>=#0                          ; if AC3>0 execute next instruction

    "..\firPPF_ASRC_stereo_bilin_decby2.asm", REMARK   at line 691: [R5505]

            This instruction will not behave correctly when it follows the MMR

              read of SP/SSP on line 690 and interrupts are enabled. Ensure at

              least 2 cycles occur between these two instructions. (see the C55x

              silicon exceptions errata; Advisory cpu_84)

    XCC     AC3>=#0                          ; if AC3>0 execute next instruction

    'Finished building: ../firPPF_ASRC_stereo_bilin_decby2.asm'

    ' '

    'Building target: c55_asrc_ccs6.lib'

    'Invoking: C5500 Archiver'

    "C:/CCS_6.1.3.00033/ccsv6/tools/compiler/c5500_4.3.8/bin/ar55" r "c55_asrc_ccs6.lib" "./asrc_dly_fix.obj" "./firPPF_ASRC_mono_bilin_decby2.obj" "./firPPF_ASRC_stereo_bilin_decby2.obj"  

     ==>  new archive 'c55_asrc_ccs6.lib'

     ==>  building archive 'c55_asrc_ccs6.lib'

    'Finished building target: c55_asrc_ccs6.lib'

    ' '

    **** Build Finished ****

    Please let us know if this resolves your issue.

    Regards,
    Mark

  • 0 in reply to Mark Mckeown
    Prodigy 250 points

    Hi Mark,

    Sorry for my late reply.

    I use C5515 which CPU revision is v3.x. But I want to combine the library build for CPU v2.x.

    I can not convert the library (built for CPU v2.x) into v3.x because of some reason.

    So, I want to use ASRC built for CPU v2.0.

    Thank you.

  • 0 in reply to Mark Mckeown
    Prodigy 250 points
    Hi Mark,
    Thank you very much building library for CPU v2.0.
    I'll check later...

    By the way, does the C55x connected audio framework have a possibility to support 24bit 96kHz audio?