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TMS320C5517: Confirm usage of I2S

Guru 24520 points
Part Number: TMS320C5517

Hi TI Experts.

Please let me confirm the following questions of relating to I2S usage on C5517.

[Question.1]
Is there any influence for the device operation by disabled the I2S function by ENABLE bit on I2SxSCTRL and setting the I2S registers like I2S0SRATE, I2S0SCTRL?

[Background]
My customer are thinking that will disable the I2S function by ENABLE bit on I2SxSCTRL register after finish to use this. So, they think that some registers values of I2S will remain after disabled the I2S function. So, they would like to know whether there is any problem by remaining those values on I2S registers.

[Question.2]
Is there any problem to set the I2SnSRATE value even though the I2S function on C5517 was set Slave? Or should customer set 0x00 values for this register in this case(Use case is slave) ?

If you have any questions, please let me know.
Best regards.
Kaka

  • Hi Kaka,

    I've forwarded this to the I2S experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • Hi,

    [Question.1]
    Is there any influence for the device operation by disabled the I2S function by ENABLE bit on I2SxSCTRL and setting the I2S registers like I2S0SRATE, I2S0SCTRL?


    The ENABLE bit says:
    "Resets or enables the serializer transmission or reception.
    0x0(Read) = The I2S Peripheral (Data transfer, clock generation, and event generate logic) is disabled and held in reset state.
    0x1 = I2S enabled"
    I don't think that toggling this bit will influence the device operation. You should be able to configure the registers & enable/disable the I2S whenever you need to issue a transaction. However you may need to follow some kind of sequence before starting a transaction through i2s, i.e. first enable the device, then write to (or read from) the tx (rx) registers.
    [Question.2]
    Is there any problem to set the I2SnSRATE value even though the I2S function on C5517 was set Slave? Or should customer set 0x00 values for this register in this case(Use case is slave) ?

    The TRM clearly states this:
    "The control block consists of internal clock generation, frame synchronization signal generation, and their control. The I2Sn Sample Rate Generator Register (I2SSRATE) contains fields to configure the framesynchronization and bit-clock dividers to drive the I2Sn_FS and I2Sn_CLK clocks when the I2S peripheral is configured as a master device"

    Even if you're able to configure the SRATE register in slave mode.. the settings will NOT take effect.

    Best Regards,
    Yordan
  • Hi Yordan,
    Thank you for your comments.
    I got it.
    If I get more questions, please let me confirm them.
    Best regards.
    Kaka