TMS320C5517: TMS320C5517: Wake-up from IDLE3 mode

Hi Massa,

I've forwarded this to the c55x design experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

Great, TNKS

BR

Massa

Hi, Tsvetolin.

You announced me you sent my question to a 55xx experts on Jun 30.

Unfortunately I can not receive the answer until now.

We need the answer.

Please send my question to them again.

Hello Massa-san
Sorry for the delay in response , the primary expert is tied up on another critical issue and has not had a chance to look at this.

A few questions from my side
1) Can you elaborate further on what is the concern and use-case.
2) Do you have this reproducible on the 5517 EVM and if so , can you share the code with us
3) You mention that setting EMIFCFG=0 makes the system work as expected - can you confirm 1) with SYSCLK=0 only scenario the DSP is actually going in IDLE3 2) Is there some program/data code in EMIF that is potentially making the behavior different or is all code in on chip RAMs?

Regards
Mukul

Hello Mukul-san

Thanks for your reply.  I will send some information of the system.

1)We want to use TMS320C5517 IDLE3 mode without RTC even we know RTC module send wake up signal to CPU.

If you can inform us that EMIF activation and wake up process are related, we want to use this method with much enough examinations without RTC.

When it's necessary to use RTC, we must redesign our PCB and software.

2)We are debugging on our original board for sound processing. 

Following codes take into IDLE3:

void idle_main(void)
{

    US16    state=0;

    /*Disable cpu interrupts*/
    IRQ_globalDisable();
    /*Clear any pending interrupts*/
    IRQ_clearAll();
    /*Disable all interrupts*/
    IRQ_disableAll();
    IRQ_setVecs((Uint32)&VECSTART);
    /*Register ISR to IVT*/
    IRQ_plug(INT0_EVENT,&interrupt_int0);
    /*Enable event*/
    IRQ_enable(INT0_EVENT);
    /*Enable cpu interrupts*/
    IRQ_globalEnable();

    *(ioport volatile unsigned *)0x1C02 = 0x77FF;    // PCGCR1
    *(ioport volatile unsigned *)0x1C03 = 0x00FF;    // PCGCR2

    *(ioport volatile unsigned *)0x1900 = 0x0001;    //RTCINTEN

    state = *(ioport volatile unsigned *)0x1C1F;
    *(ioport volatile unsigned *)0x1C1F = state & 0xfffe;    //CCR2 SYSCLKSEL=0
    state = *(ioport volatile unsigned *)0x1C22;
    *(ioport volatile unsigned *)0x1C22 = state | 0xA000;    //PCR PLLPWRDN
    *(ioport volatile unsigned *)0x0001 = 0x03EF;    //ICR idle

    WRITE_REG(OFF,C_DSP_ST);    //DSP status
    WRITE_REG(ON, F_SLEEP);        //Sleep info for FPGA
}

Following codes are for interrupt to wake up:

interrupt void interrupt_int0(void)
{
    Csl_InitConfig();

    WRITE_REG(ON, C_DSP_ST);    /* DSP->CPU boot */
    init_param(D_INITMODE);         // Initialize parameters
    CntlUty_GetRegs(D_CNTL_ACTIVE);     // Read registers
    AMR_enc_Init();         /* Init AMR endoder */
    WRITE_REG(OFF, F_SLEEP);     /* DSP->FPGA Sleep end */
    WRITE_REG(ON, F_SETUPFIN);     /* DSP->FPGA finished signal */
    g_led |= BIT0_LED;
    g_led |= BIT1_LED;
    WRITE_REG(g_led, F_LED);

    g_wakeup_count++;
    if(g_wakeup_count >= 0xffff) g_wakeup_count = 0;

    return;
}

3)SDRAM block is connected to EMIF CS0, and FPGAs are connected to EMIF CS2 and CS3.

All codes and data are in the internal RAMs.

We measured power current into DSP and read status register to confirm IDLE3 mode and Active mode.

And we confirm EMIFCFG=0 is needed to wake up from IDLE3.

Sorry for long description.

We need your advice.

Regards,

Massa.

Hi Massa-san
Thanks for the additional details on this. I have not yet had the chance to engage the key expert to look at this as he is tied up on another escalation.
I think not using RTC as a wake up source should be ok.
Have you compared the IDLE3 code example provided as part of the CSL , compared to the sequence you have shared above.

On quick glance, I think the CLKSTOP1 and 2 register (in System module/SYSCTRL module) is also missing in your code.
I wonder if that is somehow impacting the behavior with EMIFCFG=1 vs 0?

Regards
Mukul

Hi Massa-san,

Sorry for the delay.

I do not see the execution of the idle instruction in your code - it should come after writing to the ICR register (like below)
    *(ioport volatile unsigned *)0x0001 = 0x03EF;    //ICR idle
    asm("\tIDLE");
    asm("\tNOP");
    asm("\tNOP");
    asm("\tNOP");
    asm("\tNOP");
    asm("\tNOP");
    asm("\tNOP");

Refer to 1.5.5.2 IDLE3 Procedure in the C5517 TRM for steps to follow (http://www.ti.com/lit/ug/spruh16b/spruh16b.pdf)
Refer to IDLE3 example in CSL for software example (uses RTC): c55_csl_3.07\ccs_v6.x_examples\power\CSL_PowerManagement_IDLE3_Example
CSL: http://www.ti.com/tool/sprc133

I cannot think of a reason why keeping EMIFCF = 0 (not gated) would alter the behavior of your code. But it might have something to do with not using the Peripheral Clock Stop Request/Acknowledge Register. You must execute a handshaking procedure before stopping the clock to the EMIF

Refer to 1.5.3.2.2 Peripheral Clock Stop Request/Acknowledge Register in the C5517 TRM
    
When SYSCLK=0, it means that a clock is getting through to the CPU. The behavior of INT1/0 changes when there is a clock present. Refer to 1.6.2 Interrupt Timing of the C5517 TRM...

The interrupt signals on the external interrupts pins (INT0 and INT1) are detected with a synchronous negative edge detector circuit. To reliably detect the external interrupts, the interrupt signal must have at least 2 SYSCLK high followed by at least 2 SYSCLK low.
... When the system master clock is disabled (SYSCLKDIS =1), the external interrupt pins (INT0 and INT1) will be asynchronously latched and held low while the clocks are re-enabled. Once the clocks are re-enabled, the DSP will latch the interrupt in the IFR.

You are bypassing the PLL, so I expect the SYSCLK to be CLKIN. Is it 12MHz? You can probably measure it out of CLKOUT pin (with it configured). Compare with and without the EMIF clock gated...

Is CLKIN or the USB oscillator used? What is the CLK_SEL pin? What is in the Clock Configuration Register 2 (CCR2) CLKSELSTAT bit field?

Bits 3 and 2 of the IFR0 and IER0 bits must be set to 1 to enable interrupts from INT1 and INT0, respectively. Are they set? (probably)

I think you can use IDLE3 without using the RTC, but the CVDDRTC pin must always be powered by an external power source even though RTC is not used. None of the on-chip LDOs can power CVDDRTC.
You dont have to populate the RTC crystal, but you must terminate RTC_XI (to CVDDRTC) and RTC_XO (to GND) pins. You will not have access to the RTC registers in this case.

Hope this helps,
Mark