TMS320C5517: How to connect the Reserved pins

Hi Massa-san,

When in PPMODE 2 (010), all of the "Reserved" pins are pinmuxed to UHPI. Since UHPI is not useable outside of PPMODE0, the pins are "Reserved".

Best plan is to software reset the HPI peripheral and then leave its registers untouched and clock gated. Tie off the pins as recommended below. Internal pull downs can also be used as weak terminations where applicalbe (see below)

Additionally, the EBSR resets to MODE1 so avoid any bootmode that uses SPI or polling boot modes that might try to access SPI.

N3 UHPI_HINT PUDINHIBR7 (1C50h) Bit 12 IPD, disabled at reset, The pin is Hi-Z
when UHPI is in ZPOR reset or when HPIENA=0. Otherwise outputs high until writing a 1 to the HINT bit of the UHPIC register, recommend tie or pull to VDDIO, leaving IPD disabled, and avoid writing 1 to HINT bit of UHPICL. Could leave floating, as it will be driven high once peripheral is out of reset, but could oscillate when Hi-Z, during reset / peripheral reset.

P6 UHPI_HD[0] PUDINHIBR3 (1C19h) Bit 0 IPD, enabled at reset, Hi-Z when UHPI is in ZPOR reset, when there are no read accesses occurring, or when HPIENA=0, recommend to tie or pull to GND, and avoid writing any 1's to these bits in the GPIO_DAT1 register. Could rely on IPD. Might even drive low after reset.

N6 UHPI_HD[1] PUDINHIBR3 (1C19h) Bit 1 IPD, enabled at reset, Hi-Z when UHPI is in ZPOR reset, when there are no read accesses occurring, or when HPIENA=0, recommend to tie or pull to GND, and avoid writing any 1's to these bits in the GPIO_DAT1 register. Could rely on IPD. Might even drive low after reset.

P4 UHPI_HCNTL0 PUDINHIBR7 (1C50h) Bit 8 IPD, disabled at reset, Input only (terminate to avoid floating inputs), recommend tie or pull to GND to avoid contention with IPD. Could rely on IPD if enabled.

N4 UHPI_HCNTL1 PUDINHIBR7 (1C50h) Bit 9 IPD, disabled at reset, Input only (terminate to avoid floating inputs), recommend tie or pull to GND to avoid contention with IPD. Could rely on IPD if enabled.

P5 UHPI_HR_RW PUDINHIBR7 (1C50h) Bit 10 IPD, disabled at reset, Input only (terminate to avoid floating inputs), recommend tie or pull to GND to avoid contention with IPD. Could rely on IPD if enabled.

N5 UHPI_HRDY PUDINHIBR7 (1C50h) Bit 11 IPD, disabled at reset, Hi-Z when UHPI is in ZPOR reset or when HPIENA=0, recommend tie or pull to GND, Could rely on IPD if enabled. Avoid writing 1 to HRDY bit of UHPICL. Could leave floating, as it will be driven low once peripheral is out of reset, but could oscillate when Hi-Z, during reset / peripheral reset.


Regarding the "Hi-Z when UHPI is in ZPOR reset or when HPIENA=0"...
1) C5517 does not have the CFGCHIP1 register, so you cannot modify the HPIENA bit.
HPIENA is set to 1 when Parallel Port Mode of register 0x1C00 = 000, 010, 011, 100, or 101
HPIENA is set to 0 when Parallel Port Mode of register 0x1C00 = 001 or 110
So in the PPMODE 010, HPIENA will be driven static high to enable operation of the UHPI peripheral

2) ZPOR is tied to bit 7 of Peripheral Reset Register
bit 7 = PG4_RST Peripheral group 4 software reset bit. Drives the UHPI, I2S2, I2S3, UART, and SPI reset signal.
But the peripheral reset is only low until Peripheral Software Reset Counter Register (PSRCR) [1C04h] reaches 0. Then reset is released.

Hope this helps,
Mark