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TMS320C5517: Urgent: Confirm the Swtich timing from CS0 toCS2

Kaka
Guru 24520 points
Part Number: TMS320C5517

Hi TI Experts,

Please let me confirm the following question.

[Question.1]

 Can customer use the both memory CS0 and CS2 for their main application(not boot process)?

[Question.2]
If read the value from SRAM data on CS0_1 at first and next read the NOR data on CS2, how long time should cusotmer wait to asert the CS2? Is there any ouput signal that finish reading the SRAM data?
We would like to know that how should calculate in this case.
I am not familiar with External Memory. I apologize for beginner question.

We need to answer this question to our customer by end of tomorrow in Japan time. I hope to answer this by end of today in US time...
If you have any question, please let me know.

Best regards.
Kaka

  • 0
    TI__Guru**** 161600 points
    Hi,

    In general you activate CS1 to enable communication with SRAM. Perform read/write, then drive the CS1 OFF. After you deassert CS1 you can assert CS2 to enable communication with NOR.

    Have a look at Section 5.7.6 External Memory Interface (EMIF) of TMS320C5517 Data Manual, pay attention to the timing diagrams to see how CS is asserted/deasserted in different use cases.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 24520 points
    Hi Yordan,

    Thank you for your response. I could understand that user use the both memory by using the CSn pins. But I am not clear for my question No.2.

    >If read the value from SRAM data on CS0_1 at first and next read the NOR data on CS2, how long time should customer wait to assert the CS2? Is there any output signal that finish reading the SRAM data?

    Would you please answer for this question?

    Best regards.
    kaka
  • 0 in reply to Kaka
    TI__Guru**** 161600 points
    Hi,

    f read the value from SRAM data on CS0_1 at first and next read the NOR data on CS2, how long time should customer wait to assert the CS2?

    There is no specific time to wait between CSs described in the documentation.

    Is there any output signal that finish reading the SRAM data?

    Yes, there are some signals that may be used to indicate the access to an external device. See Table 4-2. EMIF Pins Used to Access Both SDRAM and Asynchronous Devices, Table 4-3. EMIF Pins Specific to SDRAM and Table 4-4. EMIF Pins Specific to Asynchronous Devices from TMS320C5517 Technical Reference Manual (SPRUH16B).

    Best Regards,
    Yordan