Hi TI Experts,
Please let me confirm the following question.
[Question.1]
Is there any specification/limitaion for Rising/falling Edge of I2S_CLK when the I2S is used as Slave mode?
Backgournd.
According to my customer, there was a case that the I2S_DX was not generated depending on the Rising/Falling Edge time. They have used the following hardware ajd register settings valuse.
- Hardware
I2S2_CLK: 2.048MHz (input)
I2S2_FS: 32KHz (input)
- Software
I2S2SCTRL: 0x8420
I2S2SRATE: 0x001C
I2S2INTMASK: 0x0003
We have gotten their captured wavefrom of I2S on osciloscope. So if you are able to check it, please conntact to me in the private message.
[Question.2]
Have you ever seen this phenomenon?
[Question.3]
If yes, would you please teach me the supposed cause?
Customer requested us to provide the answers by end of tomorrow in Japan Time. So, please provide the answers for those questions by this time. Please help us...
Best regards.
Kaka
