TMS320C5517: Urgent/Confirm the timing/condition to happen the INTRTX.

Hi Kaka-san,

Q1

The register INTRTX got set when the corresponding  EP (0-4) TX FIFO is emptied by the USB core (copied from the FIFO to the internal buffer in the USB core), not necessary the host have received it. Then, the INTMASKEDR1 will be set accordingly which will cause the USB interrupt. Once the USB ISR processes it, INTMASKEDR1 will be cleared by write the same value to INTCLRR1 (usbRegisters->INTCLRR1 = pContext->dwIntSourceL). In order to clear the  INTRTX, the EP TX FIFO needs to be filled by CPU.

Q2

There two possibilities here:

1. The SOF interrupt comes before the TX interrupt, because in ISO mode the USB host sends the IN token at the SOF, it takes some time for the TX interrupt to come in (C5517 receives IN token, USB core copies the TX data from TX FIFO to the internal buffer, sends the TX interrupt). If the SOF got processed before the TX comes in, then you will get two interrupt per ms.

2. The RX interrupt may play a role here, if the playback path is used. The RX interrupt may come in different time as the TX interrupt. If they are not processed in the same USB ISR access, then you will get two interrupt per ms.

Q3

We are in the process to make our USB audio example work on C5517 EVM at 200Mhz. We will let you know the result soon. As the reference point, all our USB examples in the CSL (USB CDC, HID, MSC and endpoints) have been tested on C5517 EVM at 200Mhz and they are all running properly.

Best regards,

Ming

Hi Kaka-san,

What I meant is that the INTRTX interrupt will be generated when the USB core (the Mentor core) copies the data from TX FIFO to its internal buffer (inside the Mentor core. it is a different area than the FIFO memory. The Mentor core will then copy the data from its internal buffer to the USB host). The TX FIFO will be free after that, therefore the potential overwrite will not happen no matter how fast the CPU runs.

The correct timing is CPU needs to fill the TX FIFO whenever the INTRTX occurs (means the TX FIFO is empty and ready to accept new data).

Here is the event sequence for USB TX transaction:

1. The TX FIFO is filled with data to be transferred.

2. The SOF interrupt received by USB device (one per ms in full speed mode).

3. The SOF interrupt is serviced by CPU (while the IN token is coming at the same time)

4. After receiving the IN token, the USB core copies the data from TX FIFO to its internal buffer.

5. INTRTX is triggered, because the TX FIFO is empty.

6. The data is transferred from USB core internal buffer to USB host (while the INTRTX is being serviced by CPU at the same time)

7. repeat 1-6. 

Ming