Hello everybody,
Our TMS320C5517 application, running @ 100 MHz, uses McBsp for trasmissions.
McBsp is programmed with internal master clock, internally generated Fsx and Clk (25 MHz),
one bit clock Fsx delay.
The following feature is requested:
Transmit through DMA 10 32 bit words at a random intervals: the 10*32 data bits must be contiguous.
Once the 10 words are sent, Fsx MUST NOT be pulsed again, until a new transfer is started.
1)Is such feature possible ?
I notice that using internal Sample Rate Generator (SGR), and writing continuosly words to DXR through CPU,
such words appear correctly in the McBsp Tx frame: however frames are continuosly repeated.
If a 1 s delay is inserted after the completion of a 10 words write cycle, Tx frames repeat themselves at
the same rate than before: the frame is however composed only by the repetition of the last words.
This occurs even in the DSP is halted.
This is compliant with with beaviour of SGR I found on TMS320C5517 Technical Reference.
In other words, is it possible to generate a 10 words frame as long 10 DXR write are completed,
and then preventing additional Fsx frames ?
TMS320C5517 Technical Reference actually grants a framing paced by DXR-XSR copy: in such case
single words are framed, and frames actually stop as soon DXR-XSR copy stop: this option is however
NOT suited to our application, as word data bits are not consective.
Every FSX clocks a spurious data bit: in other words, Fsx interval is 33 CLKX instead of 32.
If I set zero bit delay, word data bits are indeed contiguous, and Fsx interval is 32 CLKX,
but the 1 bit delay is required by the receiver.
Please note that need to use DMA : I would like to skip the use of DMA IRQ.
but whatever strategy for solving such problem is welcome.
Thank you for your attention.
Misha.
