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  • Forum Post: Re: C5506 DMA stops after 10 to 50 BLOCK cycles

    TommyG
    Brian, I would be helpful to see a screen shot of the DMA registers for the channel you are using when the transfer fails. If I understand your setup correctly you are using the Timer1 as your sync event for the transfers and that you are using the sync event to start an element transfer. Is this...
    on Sep 9, 2009

  • Forum Post: Re: LCD Display issue

    DSP_KungFu_Master
    Hello, Are the any news on the patch? is the problem in the CSL or in the Display itself? I also have a question concerning the LCD DMA transfer. As I can see from the examples and documentation DMA data transfer towards LCD is 32 bit (you set a pointer to the buffer as uint32), but the display...
    on Oct 28, 2009

  • Forum Post: LCD Controller with DMA double buffering

    DSP_KungFu_Master
    Hello, Can anybody please explain to me how double buffering works with LCD DMA controller. All provided CSL examples use only single buffering, and documentation is really scarce. All I can see is that some sort of ping-pong buffering is used. Does this mean that DMA alternatively sends first then...
    on Oct 29, 2009

  • Forum Post: DMA issue: block transfer seems never to stop / interrupts aren't executed

    Raphael19557
    Hi All, I wrote a small application based on the aic3204 sample by Spectrum. I tried to add DMA functionality, like in the USB_Stick_AudioFilter example from TI. Therefore, I configured DMA0 channel 0 to transfer data to the I2S0 Tx buffer and DMA0 channel 2 to transfer data from the I2S0 Rx buffer...
    on Dec 11, 2009

  • Forum Post: 5505 DMA I2S

    Russell Barr17013
    First thanks for the example 5505 USM_Stick_AudioFilter. It shows a good example of how to implement the I2S with ping pong buffers. If I understand correctly how the DMA auto reload works I thing there is a small issue with the implementation. When a DMA length complete interrupt occurs the DMA...
    on Dec 15, 2009

  • Forum Post: DMA McBSP setup for SPI on C5416

    Joshua Williams
    http://e2e.ti.com/support/dsp/tms320c5000_power-efficient_dsps/f/109/p/11088/43146.aspx#43146 is a similar post to my question. I am currently using CCS v3.3. As I start a new development I find it kind of disappointing that you would change the DSP/BIOS interface to not contain the graphical interface...
    on Jan 6, 2010

  • Forum Post: Re: C5506 DMA stops after 10 to 50 BLOCK cycles

    David Rick
    I am having a very similar problem to Brian's, even though I'm not using printf(). I am running continuous DMA into DARAM using element-by-element sync on INT0, which is looped back from TIM0. The transfer rate is about 5 Msps, and the buffer size is about 5k words. REPEAT and AUTOINIT are both...
    on Mar 1, 2010

  • Forum Post: Re: C5506 DMA stops after 10 to 50 BLOCK cycles

    David Rick
    Brian Willoughby Where is the textual output for LOG_prinft() sent? I've never used LOG_printf(), so I don't know, but if it goes to through the JTAG header to the emulator / debugger interface like printf() then you'll have the same problem. LOG_printf() does go through JTAG, as do other...
    on Mar 2, 2010

  • Forum Post: Re: C5506 DMA stops after 10 to 50 BLOCK cycles

    David Rick
    Brian, I'm guessing that LOG_printf() is fairly benign, because the RTDX data pipe runs as an idle process. I've always had lots of LOG_printf() calls, and the worst thing that happens is some of them get lost when the DSP gets busy. Increasing the associated buffer size in the BIOS configuration...
    on Mar 2, 2010

  • Forum Post: Re: C5506 DMA stops after 10 to 50 BLOCK cycles

    David Rick
    I can now report that my DMA stalling problem was fixed by allocating a DARAM block exclusively to the DMA destination buffer. I defined a named linker section specifically for this purpose, to prevent the linker from putting anything else in that block, and I have had no DMA timeouts since. David...
    on Mar 3, 2010

  • Forum Post: 5509A: Problem with SYNC bit in DMACSR

    WG15
    I'm using a 5509A to acquire data from an external ADC via DMA (the ADC is connected via the EMIF). An external circuit provides a trigger (synchronization event) every time a sample is taken. Normally, these triggers occur at intervals of roughly 100nSec in a burst of 1024 with several mSec between...
    on Mar 16, 2010

  • Forum Post: DSP/BIOS Audio examples for TMS320C5505 EVM

    iranovicaden
    Hello, does anybody has some working DSP/BIOS Audio examples for TMS320C5505 EVM? Audio-Out or ideally Passthrough. I'm using both CCS 3.3 and the CSL delivered with the board. If you have some, how did you create the DSP/BIOS Configuration? Using which platform-file? ti.platforms.dsk5505...
    on Mar 23, 2010

  • Forum Post: Re: 5509A: Problem with SYNC bit in DMACSR

    WG15
    Hyun, To answer your questions: 1) I'm using element synchronization mode. 2) Yes, the external triggering signal is connected to INT0. 3) I'm expecting a series of 1024 triggers at roughly 100nsec intervals (i.e., 10MHz rate). But under some situations, the other CPU that generates...
    on Mar 29, 2010

  • Forum Post: Re: 5509A: Problem with SYNC bit in DMACSR

    WG15
    Brad Griffis Have you worked around this issue? Once that event gets latched into the DMA controller it looks like you would need to do a dummy transfer in order to get rid of it. Is that what you're doing? Right - I'm currently setting up a dummy transfer to clear the unwanted request...
    on Apr 9, 2010

  • Forum Post: Re: 5509A: Problem with SYNC bit in DMACSR

    WG15
    Brian Willoughby It seems like the crux of the problem is that "under some situations, the other CPU ... has to generate 1025 pulses." If you could correct that, then it seems like all would be well. Is there any reason you can't just fix the other CPU? Looking at this from another...
    on Apr 16, 2010

  • Forum Post: Hacking the Data Converter Plugin to support other serial ADCs, and importing code to CCSv4.1.. and of course... nothing works. :(

    FastFourier
    So I'm working on a new design here at work, and the hardware engineer decided on a C5510 and a Linear Tech LTC1407 serial ADC. Since I've never used a C55xx before, and don't know how its DMA engine compares to the EDMA3 from C6000s, I thought I'd try to use the Data Converter Plugin...
    on Apr 21, 2010

  • Forum Post: DMA sync events are MIA

    FastFourier
    I'm still struggling to get a McBSP DMA chain going with my C5510. The McBSP is working great when I manually read it with MCBSP_read32( hMcbsp ); When I try to trigger DMA transactions off of the RSYNC events from this McBSP port, everything goes awry. :( Here's the situation... McBSP0...
    on May 12, 2010

  • Forum Post: Re: DMA sync events are MIA

    TommyG
    FF, What versions of CCS, BIOS and Code Gen are you using? Can you provide register dump of McBSP and DMA channel you are using? You never mention how you setup the McBSP. Is it configured to generate the sync event to the DMA? Regards.
    on May 24, 2010

  • Forum Post: Re: DMA sync events are MIA

    FastFourier
    And here's the DMA setup. // Set our DMA channel 1,0 depending on which is correct. adc->uiDmaChanRx = adc->nWhichADC; // Open the DMA channel and save off the handle. adc->hDmaRx = DMA_open( adc->uiDmaChanRx, DMA_OPEN_RESET ); // Check for valid. if( INV...
    on May 25, 2010

  • Forum Post: Re: DMA sync events are MIA

    FastFourier
    I was trying to generate SYNC events from the McBSP to the DMA engine on RRDY. I assumed that happened when I set the McBSP SPCR1 RRDY interrupts generation, and then set the DMA to SRC off of my McBSP DRR1. Is there an additional step I'm not aware of? If so, I'd love to know where that's...
    on May 25, 2010

  • Forum Post: Re: DMA sync events are MIA

    FastFourier
    Ha! Thanks, you're right. DMA setup for DMA_CHAN0 (DMAGCR, GSCR, GTCR) 0x000E00 : 0x08 ---- ---- ---- (DMASCDP0 through DMACDFI0 ) 0x000C00 - 0x000C0F : 0x0E 0x41 0x0A 0x40 0x00 0x00 0x08 0x04 0x71 0x04 0x00 0x00 0x02 0x00 0x00 0x00 And for completeness, the McBSP setup...
    on May 25, 2010

  • Forum Post: Re: DMA sync events are MIA

    FastFourier
    SUCCESS! WHoo hoo! I needed to change two things to get this all to work. 1.) Right before I called DMA_start(), I had to read DMACSR to clear it and enable any new events. BUT, I had to read it into a volatile int, so that the read wouldn't get optimized away. Also, in my ISR, I changed that...
    on May 27, 2010

  • Forum Post: Re: 5515 Half buffer DMA interrupt

    TommyG
    di-sk, There should be a DMA Peripheral Reference Guide (PRG) for the C5515, but I don't see it. Maybe it is not released yet. There is a mode in the C5515 DMA to setup Ping-Pong buffers which should give interrupts when either Ping or Pong buffer is available. You can get details by looking at...
    on Jun 30, 2010

  • Forum Post: C5510 DMACDAC unexpected results...

    FastFourier
    I am using the C5510A with some serial ADCs sampling I/Q of a pair of tuners. I'm doing DMA transactions into ring buffers that I'm filling and processing. I'm wanting to monitor my DMA transactions as they cycle through my ring buffer. i.e. I want to know exactly what address the DMA...
    on Jul 13, 2010

  • Forum Post: Re: User Guide exclusively for C5505/15 DMA programming setup and working ?

    TommyG
    AV, The DMA Peripheral Reference Guide does not seem to be released yet. Have asked C5000 Product Team for projected release date. In the mean time you can get started using the TMS320VC5505 DMA PRG ( http://www-s.ti.com/sc/techlit/sprufo9 ). The DMA controller for the C5505/15 has some differences...
    on Aug 24, 2010
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