The datasheet for the 6472 claims that PLL3 is fixed at a 20x multiply, but I am currently running my custom board with a 19x multiply. The frequency of the DDR clock matches what I would expect. Also my DDR accesses are much more reliable at this slightly lower speed. Is the documentation for PLL3 incorrect for the 6472?
The datasheet is correct. It is X20 clkin. Please double check the clock in your side.
After writing to the offset for the multiplier register, I do indeed have PLL3 running at a 19x rate. 25MHz in, ~237MHz out.
Which register you are writting to? you are not supposed to write to any multiplier register of PLL3 since it has fixed multiplier. If you have clk3 at 25MHz, you should see 250MHz ddr clock without writting to any register of PLL3.
We verify the ddr clock before.
Yes, that is true, without any modifications PLL3 will output a 250MHz clock for the DDR. But we had some issues with our DDR interfaces and in an attempt to help debug, we wrote to the "non-existant" multiplier register to slow the interface down. This did work, our clock rates slowed as we expected, and we were able to reliably read and write memory after dropping the multiplier down to 18x. We have another design which still requires more testing, but at full rate it was showing issues as well.
Is this hidden feature supposed to be there? Will it always be there? I'm working on seeing if I can tweak my series termination values to get the DDR running at the full rate, but if that does not work, will using PLL3 to ease the clock rate back continue to be a solution?
No. when you try to eash the clock rate, please lower down the clkin input instead of reconfigure the PLL3 controller.
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