C64x Multicore DSP Forum - Recent Threads

EDMA3 for ping-pong buffer

Jiajin An1 — Tue, 14 May 2013 21:58:04 GMT

I use C6474.

The CSL example <c6474_CSL_Rel_03_03_01\C6474\csl_c6474\example\edma\edma_ping_pong_xfer_reg5> works.

I can compile it and then run it. Then I can see the following output:

Running Edma Example
<<EXAMPLE PASSED>>: Edma Ping Pong Buffer Transfer Passed

This example is designed to firts do DMA for ping buffer, then do DMA for pong buffer, then check the results.

In real application, we have to repeat the above operations. In other words, we want EDMA ping, then EDMA pong, then EDMA ping again, and then pong again, ...

I tried to do so by copying line 307-381 to line 382 in Edma_ping_pong_xfer_reg5.c.

When I ran it. The first ping-pong edma still worked. However, when it started to do the 2nd edma for ping buffer, it stoped in the Polling loop on interrupt bit 0.

TMS320C6x Evaluation Module

Reza Zolhayat — Sat, 25 May 2013 01:48:45 GMT

Hello,

I have just purchased TMS320C66x Evaluation Module and install DVD including code composer version

5.2.1.00018.

I followed all instruction inside the READ_ME file to install it properly.

Now, once I attempt to debug it says licence expired or I am using Unlicensed program.

Could you tell me what i should do?

Thank You.

Reza Zolhayat,P.Eng.

c6474 second boot

zhilin song — Thu, 23 May 2013 09:27:23 GMT

Hi everyone，

I am using c6474, I want to switch directly from the set of code to another set of code, without the need for reset, how should I do?

Boottable code stored in two different areas ddr.

Thanks

Which SPn_ERR_STAT errors cause SPn_ERR_RATE's ERROR_RATE_CNT bits to increment

Eddie3909 — Thu, 02 May 2013 00:28:23 GMT

C6472, DIO lib 1.1.0 DirectIO

Which SPn_ERR_STAT bits cause SPn_ERR_RATE's ERROR_RATE_CNT bits to increment?

And when the SPn_ERR_THRESH is reached, is that when bit 8 "Error on Port 0" in ERR_RST_EVNT_ICSR is set?

What happens if its a fatal error (i.e. bit 2 of SPn_ERR_STAT). Is bit 8 "Error on Port 0" of ERR_RST_EVNT_ICSR set immediately?

Cheers2u

ldotp2_intrinsic

Mushtaq Syed — Mon, 13 May 2013 23:44:27 GMT

Hi:

I have questions about the dotp2 and ldotp2 intrinsics. Below is the description from Table 2.7 (Table 2−7. TMS320C64x/C64x+ C/C++ Compiler Intrinsics (Continued)) of SPRU198K.

Based of the description of dotp2, is it correct to say that the accumulation is 32 bits.

Silimalry, based on the description of ldotp2, the accumulation is 64 bits.

In both cases we have products of 16 bit numbers.

Thanks a lot!

Cheers,

Mushtaq

int _dotp2(int src1, int src2); DOTP2

double _ldotp2(int src1, int src2); LDOTP2

The product of the signed lower 16-bit values of

src1 and src2 is added to the product of the

signed upper 16-bit values of src1 and src2.

The _lo and _hi intrinsics are needed to access

each half of the 64-bit integer result.

Software Tool Kit for Medical Diagnostic Ultrasound

Wissam Marrouche — Mon, 18 Feb 2013 11:24:08 GMT

I have the TI Embedded Processor Software Tool Kit for Medical Diagnostic Ultrasound CD version 2. I want to join the following ultrasound packages: rxbf, rfdemod, bpu, dpu and scu into one functional block that takes raw data as input and produce a raster image. I am finding difficulties gluing all the modules together.Is there a sample code of a top level module that combines all these functions? Note: I am using code composer to download on TI 64x DSP.

dropped interrupt problem -cpu interrupt 13 drop system event 44 (TINTHI5) on 6488

weiqiang li1 — Wed, 08 May 2013 10:06:07 GMT

I am developing multithreaded software for C6488 platform. Now I have encountered the problem of CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTXSTAT which value equal to 0x2C0D0001. This indicates that interrupt 13 drop event 44 . In my software I bind timer 5 high(TINTHI5) to CPU interrupt 13.

Could any one tell me a clue what could be the possible reason for this dropped interrupt.

Should I mask the dropped interrupt with (CSL_IntcRegsOvly)CSL_INTC_0_REGS)->INTDMASK register?

Thanks a lot!

What can cause the "Port unrecoverable error": bit 2 in SPn_ERR_STAT?

Eddie3909 — Wed, 01 May 2013 22:34:05 GMT

Is there a listing of what can cause the "Port unrecoverable error": bit 2 in SPn_ERR_STAT?

Cheers2u

Getting "Error detected on Port 0" bit set in ERR_RST_EVNT_ICSR

Eddie3909 — Wed, 01 May 2013 22:33:09 GMT

C6742. Diolib 1.1.0

When we get b8 set in ERR_RST_EVNT_ICSR, Table 40 in SPRUE13J says that this could be due to bits SPn_ERR_STAT b2, b16, b20, b24, and b25.

Are there any other that are tied to the ERR_RST_EVNT_ICSR bit 8?

Are the SPn_ERR_STAT bits hardwired to ERR_RST_EVNT_ICSR bit 8?

Is there a register you can use to disable the wiring of SPn_ERR_STAT bits to ERR_RST_EVNT_ICSR bit 8?

Cheers2u

creating the video codec library in c64x

esh waran — Thu, 18 Apr 2013 05:40:31 GMT

Hi everybody ,

i like to develop Vp8 codec library in c64x processor.I'm beginner in c64x processor.

could anyone help me through docs ,links or any suggestion ?

regards

Eshwaran

I2C read using CSL

khaled saab — Fri, 05 Apr 2013 18:05:41 GMT

Hi,I'm using C6472, CCS3.3, and I would like to write a simple I2C read routine.

I tried the example code that came with the CSL library and it worked fine (write and read back in loopback mode).

I need a simple read. I tried to modify the example code with no success. I tried other examples from the web with no success either.

Here is partial code. I removed many of the status return checks to simplify the reading.

My problem is that the read register (RRDY bit) is never ready! Do I have to start by transmitting the slave address, or its is sent automatically? Please help.

void I2C_init(void) {

   CSL_Status        status;
   CSL_I2cObj      i2cObj;
    CSL_I2cHwSetup hwSetup;

    hwSetup.mode           = CSL_I2C_MODE_MASTER;
    hwSetup.dir            = CSL_I2C_DIR_TRANSMIT;
    hwSetup.addrMode       = CSL_I2C_ADDRSZ_SEVEN;       //7bits addressing mode
    hwSetup.sttbyteen      = CSL_I2C_STB_DISABLE;       //DISABLE == disable start byte (Normal mode)
    hwSetup.ownaddr        = CSL_I2C_SLAVE_ADDR;       //address used to talk to this DSP chip
    hwSetup.ackMode        = CSL_I2C_ACK_ENABLE;
    hwSetup.runMode        = CSL_I2C_FREE_MODE_DISABLE;   //DISABLE == stop at breakpoint
    hwSetup.repeatMode     = CSL_I2C_REPEAT_MODE_DISABLE;//DISABLE == no repeat mode
    hwSetup.loopBackMode   = CSL_I2C_DLB_DISABLE;       //DISABLE == digital loopback mode is disabled
    hwSetup.freeDataFormat = CSL_I2C_FDF_DISABLE;       //DISABLE == use 7/10bits addressing mode
    hwSetup.resetMode      = CSL_I2C_IRS_ENABLE;        //ENABLE == put in reset
    hwSetup.bcm            = CSL_I2C_BCM_DISABLE;       //DISABLE == disable back compatibility
    hwSetup.inten          = 0x00;                     //interrupt enable mask
    hwSetup.clksetup       = &clksetup;                   //prescaler and clock setup

    CSL_i2cInit(NULL);
    sI2C_Handle = CSL_i2cOpen(&i2cObj, CSL_I2C, NULL, &status);
    CSL_i2cHwSetup(sI2C_Handle, &hwSetup);
    CSL_i2cHwControl(sI2C_Handle, CSL_I2C_CMD_OUTOFRESET, NULL);
}

uint16_t I2C_read(uint16_t endPoint, uint8_t *data_p, uint16_t length) {

     int16_t timecount, timeout = 0x1000;
   CSL_Status status = CSL_SOK;
    uint16_t response;
   uint32_t BbResponse;   //busy bit
    uint32_t cmd_arg;
   uint8_t endPointAddress;

   // set address of the slave device
    endPointAddress == 0x40;
    CSL_i2cHwControl(sI2C_Handle, CSL_I2C_CMD_SET_SLAVE_ADDR, &endPointAddress);
    CSL_i2cHwControl(sI2C_Handle, CSL_I2C_CMD_SET_DATA_COUNT,&length);

   // Configure Options for Receiving - Master Reciever mode
// CSL_i2cHwControl(sI2C_Handle, CSL_I2C_MODE_MASTER,NULL); //master
    CSL_i2cHwControl(sI2C_Handle, CSL_I2C_CMD_DIR_RECEIVE,NULL); //receive
    CSL_i2cHwControl(sI2C_Handle, CSL_I2C_CMD_ENABLE,NULL); //enable
    CSL_i2cHwControl(sI2C_Handle, CSL_I2C_CMD_START,NULL);   //start

   // Wait for the transfer to start
    do {
        CSL_i2cGetBusBusy(sI2C_Handle,&BbResponse);
    } while(BbResponse != 1);

    while(length) {     //receive all data words
        CSL_i2cGetHwStatus(sI2C_Handle, CSL_I2C_QUERY_NACKSNT, &response); //check NACK
        if ( response != 0x0001 ) {

            CSL_i2cGetHwStatus(sI2C_Handle, CSL_I2C_QUERY_ACS_RDY, &response);   //check ARDY
            if (response != CSL_I2C_ACS_READY ) { //we still have more data to read

                CSL_i2cGetHwStatus(sI2C_Handle, CSL_I2C_QUERY_RX_RDY, &response);   //check RRDY (can't get past this point)
               if ( response == CSL_I2C_RX_READY ) {
                    CSL_i2cRead(sI2C_Handle,data_p++); //Read Data
                    length --;

                   // Clear Receive Ready field
                   do{
                       cmd_arg=CSL_I2C_CLEAR_RRDY;
                       CSL_i2cHwControl(sI2C_Handle,CSL_I2C_CMD_CLEAR_STATUS,&cmd_arg);
                       CSL_i2cGetHwStatus(sI2C_Handle, CSL_I2C_QUERY_RX_RDY, &response);
                   }while(response==CSL_I2C_RX_READY);
               }//if Rx ready
            }//if ARDY: we still have data to read

           // Check for Arbitration Lost
           CSL_i2cGetHwStatus(sI2C_Handle,CSL_I2C_QUERY_AL, &response);
           if ( response == CSL_I2C_ARBITRATION_LOST ) {
               return 1001;
           }

            /* Check for NACK */
            CSL_i2cGetHwStatus(sI2C_Handle,CSL_I2C_QUERY_NACKSNT, &response);
            if ( response == 0x0001 )   return 1002;

            /* Check for Register Access Ready - Good Condition */
            CSL_i2cGetHwStatus(sI2C_Handle,CSL_I2C_QUERY_ACS_RDY, &response);//why ARDY!=1?
           if ( response == CSL_I2C_ACS_READY ) {
               do{
                   cmd_arg=CSL_I2C_CLEAR_ARDY;
                   CSL_i2cHwControl(sI2C_Handle,CSL_I2C_CMD_CLEAR_STATUS,&cmd_arg);
                   CSL_i2cGetHwStatus(sI2C_Handle,CSL_I2C_QUERY_ACS_RDY, &response);
               }while(response == CSL_I2C_ACS_READY);
                return 0;
           }
        } // if NACK
   } //for all data

    // I2C Timeout
   return 2002;
}

Theoretical clock cycles vs. measured time

Andrey56137 — Fri, 08 Oct 2010 21:03:51 GMT

We are in the process of verifying theoretical cycle time calculations for a convolution function, based on information from the generated asm file.

Following results and questions pertain to the attached file conv.c.txt and a section of the generated conv.asm file (please see below).
conv.c implements a basic convolution function.

Our setup details are :
- EVM6472, used to run .out file generated from a SYS/BIOS based
project
- CCS v4.2
- SYS/BIOS (BIOSv6)
- CGT v7.0.3

There appears to be a mismatch in timing measurements, with "actual run time" being about 9 times the "computed run time".

From the C code,
Number of outer loop iterations = x_len + h_len = 196000+36000 = 232000
Number of inner loop iterations = h_len = 36000

From asm file, Cycle time for software pipelined loop is

Total cycles (est) = 10 + trip_cnt * 2, with 2 DOTP2 instructions for a SINGLE SCHEDULED ITERATION.

Hence, computed run time = x_len*(10+trip_cnt*2),
trip_cnt = h_len/4 (2 DOTP2's per iteration)

Therefore,
Computed run time = x_len*(10+h_len/2) = 4178320000 cycles.
At 700Mhz, this would correspond to a time of 6s (approx).

However actual run time of the program was determined to be ~52 s. Run time was calculated by inserting SYS/BIOS (BIOS6) Clock_getTicks() calls right before and immediately after the outer loop. Also, we made sure that interrupts were disabled during execution of the loops, this had no effect on run time measured.

(1) Is there something wrong with how "Computed run time" is being calculated or how we are measuring "Actual run time" ?

(2) As part of the Software Pipeline information, the compiler outputs a line that reads something like "ii = 2 Schedule found with 6 iterations in parallel". Does the word "iterations" in the above phrase correspond to actual inner loop iteration in c code ? If so, is the number 6 in the above example, to be used in computing "expected run time" ?

Thank you in advance for your help.

Andrey

Relevant part of the .asm file:

$C$DW$L$_conv$6$E:
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line                 : 78
;*      Loop opening brace source line   : 78
;*      Loop closing brace source line   : 84
;*      Loop Unroll Multiple             : 4x
;*      Known Minimum Trip Count         : 4
;*      Known Max Trip Count Factor      : 4
;*      Loop Carried Dependency Bound(^) : 1
;*      Unpartitioned Resource Bound     : 1
;*      Partitioned Resource Bound(*)    : 2
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0
;*      .S units                     0        0
;*      .D units                     1        1
;*      .M units                     1        1
;*      .X cross paths               1        1
;*      .T address paths             1        2*
;*      Long read paths              0        0
;*      Long write paths             0        0
;*      Logical ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          1        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             0        0
;*      Bound(.L .S .D .LS .LSD)     1        1
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 2 Schedule found with 6 iterations in parallel
;*
;*      Register Usage Table:
;*          +-----------------------------------------------------------------+
;*          |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;*          |00000000001111111111222222222233|00000000001111111111222222222233|
;*          |01234567890123456789012345678901|01234567890123456789012345678901|
;*          |--------------------------------+--------------------------------|
;*       0: |   *****                        |    *****                       |
;*       1: |      **                        |    ** **                       |
;*          +-----------------------------------------------------------------+
;*
;*      Done
;*
;*      Loop will be splooped
;*      Collapsed epilog stages       : 0
;*      Collapsed prolog stages       : 0
;*      Minimum required memory pad   : 0 bytes
;*
;*      Minimum safe trip count       : 1 (after unrolling)
;*      Min. prof. trip count (est.) : 2 (after unrolling)
;*
;*      Mem bank conflicts/iter(est.) : { min 0.000, est 0.000, max 0.000 }
;*      Mem bank perf. penalty (est.) : 0.0%
;*
;*
;*      Total cycles (est.)         : 10 + trip_cnt * 2
;*----------------------------------------------------------------------------*
;*        SINGLE SCHEDULED ITERATION
;*
;*        $C$C35:
;*   0              LDDW    .D2T2   *B7++,B5:B4       ; |78| ^
;*   1              LDNDW   .D1T1   *A6++(8),A5:A4    ; |78| ^
;*   2              NOP             4
;*   6              DOTP2   .M2X    B4,A4,B6          ; |78| ^
;*     ||           DOTP2   .M1X    B5,A5,A3          ; |78| ^
;*   7              NOP             3
;* 10              ADD     .L2     B6,B8,B8          ; |78| ^
;*     ||           ADD     .L1     A3,A7,A7          ; |78| ^
;*     ||           SPBR            $C$C35
;* 11              NOP             1
;* 12              ; BRANCHCC OCCURS {$C$C35}        ; |78|
;*----------------------------------------------------------------------------*
$C$L5:    ; PIPED LOOP PROLOG
;          EXCLUSIVE CPU CYCLES: 11

           SPLOOPD 2       ;12               ; (P)
||         MVC     .S2     B4,ILC

;** --------------------------------------------------------------------------*
$C$L6:    ; PIPED LOOP KERNEL
$C$DW$L$_conv$8$B:
;          EXCLUSIVE CPU CYCLES: 2
           LDDW    .D2T2   *B7++,B5:B4       ; |78| (P) <0,0> ^
           LDNDW   .D1T1   *A6++(8),A5:A4    ; |78| (P) <0,1> ^
           NOP             4

           DOTP2   .M2X    B4,A4,B6          ; |78| (P) <0,6> ^
||         DOTP2   .M1X    B5,A5,A3          ; |78| (P) <0,6> ^

           NOP             2

           SPMASK          L1,L2
||         ZERO    .L1     A7                ; |78|
||         ZERO    .L2     B8                ; |78|

           SPKERNEL 4,1
||         ADD     .L2     B6,B8,B8          ; |78| <0,10> ^
||         ADD     .L1     A3,A7,A7          ; |78| <0,10> ^

$C$DW$L$_conv$8$E:
;** --------------------------------------------------------------------------*
$C$L7:    ; PIPED LOOP EPILOG
;          EXCLUSIVE CPU CYCLES: 9
;** --------------------------------------------------------------------------*
$C$DW$L$_conv$10$B:
;          EXCLUSIVE CPU CYCLES: 12
           NOP             1
           MV      .L1X    B8,A3
    .dwpsn    file "../conv.c",line 86,column 9,is_stmt
           ADD     .L1     A7,A3,A3          ; |86|
           SHR     .S1     A3,15,A3          ; |86|
           STH     .D1T1   A3,*A24++         ; |86|
    .dwpsn    file "../conv.c",line 70,column 15,is_stmt

           SUB     .L2     B0,1,B0           ; |70|
||         ADD     .S2     2,B31,B31         ; |70|

   [ B0]   BNOP    .S1     $C$L4,4           ; |70|
|| [ B0]   ADD     .L2     B31,B2,B4
|| [ B0]   MV      .S2X    A25,B7

   [ B0]   MV      .L1X    B4,A6             ; Define a twin register
           ; BRANCHCC OCCURS {$C$L4}         ; |70|
$C$DW$L$_conv$10$E:
;** --------------------------------------------------------------------------*

Occasional data errors in memory writes?

Michael P — Wed, 17 Apr 2013 15:27:04 GMT

I wrote a small executable to load into the two TMS320C6474 chips on a custom board (based roughly on the two-DSP eval module from Spectrum Digital). It was meant primarily as a board assembly test tool, but its results so far mostly work against that purpose...

The executable resides in core 0's L2RAM. It initializes the PLLs, sets MAR16-MAR18 and MAR128-143 (each chip has 256 MB of DDR2 attached), and then repeatedly writes and reads back a pseudo-random pattern to (a) the unused portion of core 0's L2RAM, (b) core 1 and core 2's L2RAM, (c) core 1 and core 2's L1D RAM, and (d) the DDR2. It stores its findings at a fixed address (in core 0's L2RAM) that is then read over SRIO or JTAG.

On some DSPs, the readback occasionally sees the wrong value -- although I think the failure occurs during the write because a read of the faulting address still sees a wrong value after the rest of that contiguous block is read back and checked. This occurs both on our board and on a Spectrum Digital eval module (on the eval module, I comment out the PLL initialization, and let the standard GEL file set those up, because the system clocks are a different frequency) although the frequency of failure varies greatly from chip to chip.

How can we determine the root cause of the mismatches?

The frequency might be related to the PLLs: For example, one chip saw five L2RAM mismatches out of 27 full passes through the memory when running at 61.44*16 (=983) MHz; the other chip on the same board sees no mismatches. If I use the no-PLL-initialization image, the failing chip sees two L2RAM mismatches out of 31 passes (but takes 13 times as long to run -- see also http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/p/216699/907077.aspx), and the other chip is still all clear.

It is possibly influenced by the addresses involved: Two failing chips (one on an eval module, one on the custom board) both saw mismatches at 0x128843F8 (and both saw the same wrong value there: 0x9092E900 rather than 0x9092E9A4); both saw mismatches at 0x12884A7C (reading 0x00000000 rather than 0x90908AC5); both saw mismatches at 0x12884BCC (but with different values: 0x00000000 or 0x80000A00 rathern than 0x9090E2F8); and the chip on the eval module saw an additional mismatch at 0x12801114 (0x0478461F instead of 0x9284461F). While all of those were related to core 2's memories, one (custom) board saw a mismatch in core 1's L1RAM in 13 consecutive passes, another saw a mismatch in DDR2 as well as in core 2's L2RAM.

It does not seem to be related to the chip's position on the board: Roughly half of the mismatches occur with "DSP 0" and half with "DSP 1", although those were mostly one mismatch out of 13 full passes through memory; a larger population of test failures might show some (presumably weak) pattern.

VLIB Dowload Information

searKing chan — Mon, 22 Apr 2013 18:32:28 GMT

您好！能发我一份vlib2.2吗？471030698@qq.com

C6474 bootloader PLL mode?

Michael P — Wed, 26 Sep 2012 14:41:45 GMT

Table 31 in SPRUEC6G says "For all bootmodes, the PLL is set to x16 mode." This does not correspond with what I see on a silicon revision 2.1 DSP (DEVID.VARIANT=4).

If I connect an emulator to a DSP using boot mode 9 (DEVSTAT register value 0x00000022), trigger a warm reset for the DSP, and let the bootloader run for a while -- with no SRIO transactions being sent to the DSP -- I see the PLL1 registers stay in their reset values (PLLCTL.PLLEN=0, PLLM.PLLM=0, and so forth).

Is this the expected behavior? Is the application responsible for programming the PLL, even if it wants x16 mode?

VLIB functions not behaving correctly !?

benoit goas — Thu, 11 Apr 2013 09:34:37 GMT

Hi,
we just started using some VLIB 2.2 functions for one of our codes on C6474, but we have some problems with the way they behave.

For example, about the function VLIB_updateEWRVarianceS16 :
- Its test function VLIB_testUpdateEWRVarianceS16 passes correctly (linked with vlib.l64p renamed as .lib for CCSV5)
- It’s supposed to compute updatedVar = (1 – weight) × previousVar + weight × (newestData – previousMean)² with a weight coded as SQ0.15 (VLIB 2.2 SPRUG00E – August 2011)
- Seeing its results, it uses the weight as “0.18”, or 0.15/8, or always starting with 3 zeros before the 15 digits given, so not as a true 0.15
- Also according to our results, that weight is taken modulo “0.5” : giving half its value range is the same as giving 0
- The function calculated appears to be updatedVar = (1 – weight) × previousVar + (weight/2) × (newestData – previousMean)² (checked against manual and Excel computations). It seems to also be the case when used in its test function (see computation for the pixel value at 12, giving 0x4f instead of the theoretical 0x50 we computed), but it's hard to say when so few computations are done in that test function (more than half of them are masked, and the delta of 1 could be a rounding issue)

Is this the expected behavior of the function?
Is there any complete documentation describing this?

Right now, with both exponential update functions and the subtractBackgroundS16, we get a variance converging to values really close to 0 and most pixels of the images get flagged as foreground, even with both thresholds at their maximum value, which doesn’t make sense…

I hope we'll be able to understand these VLIB functions more with your help,
B. GOAS

PrebuiltExecutables6678 for Ultrasound imaging 4 Demo

Ahmad Masri — Fri, 12 Apr 2013 06:57:38 GMT

Hello

I cannot seem to find the PrebuiltExecutables6678 for Ultrasound imaging 4 Demo, it is the final step in the test demo, and i cannot find the files anywhere in the TI Support site

i am a 6474 beginner, want to know how to build phisal layer code on the dsp ...

Shinny Guo — Tue, 02 Apr 2013 03:08:33 GMT

how to use the ccs to build a project with 3 cores,

and how to write some diver code to boost the dsp,

i have looked into the 'C6000™ Multicore DSPs' in the wiki, but not found what i need,

if someone know the answers, please let me know, thanks

L1D and LL2 cache coherency when using EDMA3

SNBANIK — Tue, 02 Apr 2013 15:58:11 GMT

Processor Used: c6472.

We have a situation where we suspect we could be hitting a L1D to L2 cache coherency issue but not sure.

We use all of L1D as cache. We have a (temporary) processing buffer (significant size) in LL2. The final output buffer is in DDR2. We use EDMA3 to transfer the processed output from LL2 to DDR2 and then clear the LL2 for next round of processing.

We are seeing an intermittent artifact and What we are not sure is if somehow L1D cache could be overwriting the cleared LL2 buffer (LL2 got written over by the L1D cached contents because it needed a new line to be assigned to L1D cache).

However reading SPRU871 it doesn't look like that should be happening.

This is what I am referring to in SPRU871.

3.3.6 Cache Coherence Protocol

The C64x+ L1D cache remains coherent with respect to DMA activity in L2 RAM. To support this
paradigm, the L1D cache accepts cache coherence commands arriving from L2.

3.3.6.1 L2 to L1D Cache Coherence Protocol

To support L1D cache coherence with respect to DMA/IDMA traffic in L2 RAM, the L1D controller supports
two cache coherence commands arriving from L2: snoop-read (SNPR) and snoop-write (SNPW). The L2
only sends these snoop commands, when necessary, in response to DMA and IDMA activity in L2 RAM.
Snoop-read is sent to L1D when L2 detects that the L1D cache holds the requested line, and that the line
is dirty. L1D responds by returning the requested data.
Snoop-write is sent to L1D when L2 detects that the L1D holds the requested line. It does not matter if the
line is modified within L1D. The L1D updates its contents accordingly.

Will appreciate any help you can provide in clarifying the above.

Thanks,

Somnath Banik

VCP2 Questions

Sezer Kutluk — Wed, 16 Jan 2013 09:04:41 GMT

Hi,

I am having trouble using VCP2. I have an example project (based on TCI6482TCP2VCP2BER by Sebastien Tomas) and it works. But state metrics are re-initialized before decoding each frame. I need to use the state metrics continually, because the data stream I get is encoded without resetting the metrics (as if it is a big message). So, when I am using the example project for decoding this data, first bytes of some messages are decoded wrong.

I have some questions regarding the example project.

1) What is the traceback length in this example? What parameter is it?
2) What is frame length? (length of the frame to be decoded?)
3) Are these lengths in bytes or bits?
4) How to prevent re-initializing the state metrics? Which parameters, registers, definitions should I alter? (I guess, what I want to use is convergent traceback mode).

I am using C6474. The document SPRUG20B is not so helpful to me, probably because I am a total newbie.

Thank you.

Decoding a Long Frame using VCP2

Sezer Kutluk — Tue, 02 Apr 2013 11:47:17 GMT

Hello,

I want to decode a never-ending data stream using VCP2 on C6474. The data I need to decode is encoded without resetting the state metrics, so we can consider it as one long message. I have to decode this frame by frame using the state metrics continually. The implementation that I have found and been able to use decodes only a frame of some length. When I use this for my problem, the first and last some bits are corrupted.

I read the documents and the example codes, but I could not make it work in this way. Moreover, I could not understand what the traceback length is, how to change it, where the state metrics are stored, how to use the sliding window concept, etc. Combining these with the lack of DSP programming experience and enough coding/decoding/Viterbi knowledge, I cannot develop any reasonable solution.

I have found a workaround but it is not theoretically proven. To decode a frame of length n bits, I feed the decoder by adding redundant m bits from each of the previous and the next messages. So when I decode (m + n + m) bits, the middle n bits are the desired message without any corruption. Is this reasonable? Even if it is, the redundancy is really high since m should be at least the traceback length. Since the constraint length is 7 and coding rate is 1/2, the redundancy is 5*7*2*2 symbols per a frame of 250 decoded bits (per second). So I am after a more proper way.

Any suggestions and comments would be much appreciated.

C6472 SRIO (aka RapidIO) Packet Retrys when FPGA sends data to L2

Eddie3909 — Tue, 26 Mar 2013 01:11:10 GMT

Configuration:

- C6472, DIO lib 1.1. Rapid IO 3.125 Mbps

- FPGA sending NWRITE packets to DSP L2

The DSP is issuing packet retrys to the FPGA on Port 1 who's target is L2. Our experiments show that we need more than 2 usec between each SRIO IO packet to prevent retrys. (huge when a full payload packet is about 0.9 usec).

Transfers to Port 0 never issue retrys, but we suspect this is because it targets DDR thats not as active as L2.

Since we are doing some serious number crunching in the same L2 that Port1 targets, I'm wondering if its possible to give the SRIO peripheral's DMA higher priority. There are the megablock bandwidth management registers L2DCPUARBU and MDMAARBE. The PRI for the former is 1 and the latter is set to 7 (lowest priority).

Would changing the L2DCPUARBU PRI to 3 and MDMAARBE to 2 invert the priorities so that the SRIO DMA can will not be held off and issue retrys?

Or would it be better to mess with MAXWAIT somehow?

Or perhaps I'm barking up the wrong tree?

My hope is that by changing priorities, the rapid IO retrys will subside giving proof that they are being sent because L2's bandwidth is being maxed out. Its not a fix, but more diagnostic. I think the fix would be to move the target to DDR and then have a DMA setup to move to L2 as needed.

Cheers2u

About MSGQ

Kaiqi Yang — Sun, 12 Jun 2011 09:38:44 GMT

We know that MSGQ is a variable-length messaging protocol,is there any size limit of the message in MSGQ?

HyperLink interface with TI DSP Processors and FPGA's

Chris Satchell — Thu, 21 Mar 2013 10:23:30 GMT

I understand that the usual place to position AC coupling (or DC blocking) capacitors on a high speed serial interface is in the TX path. In fact the PCIe specification suggests these are placed in the Tx path between the PCIe serial output pins and the PCIe connector, rather than close to the Rx pin particularly for Signal Integrity considerations.

However, in TI HyperLink schematics or EVM boards the DC blocking capacitor appears to be placed nearest the Rx pin of the interface. A particular example can be seen in this EVM board schematic on p.12 where at the bottom of the page the Hyperlink schematic is drawn.

http://wfcache.advantech.com/support/6670/3/TMDXEVM6670Lx_EVM_REV_3_0_DSN.pdf

As I understand it, another purpose of the capacitor is to detect the presence of the receiver. During the initialization, the common mode voltage on the transmitter charges the capacitor. The presence or the absence of the receiver is detected using this charging time constant. This allows the transmitter to shut down if the receiver is absent because it may be on a plug-in board and it is not present. Clearly if the capacitors are nearest the Rx pins (and the board is not plugged in) this method of detection is not possible.

Is there a specific placement necessary/required for the DC blocking capacitors on a HyperLink interface - and if so please could you explain the reason. Certainly the PCIe specification dictates that the capacitors are placed close to the Tx pins.

Many thanks

Chris S.

polyphase filters and circular buffers in c64

Amsal Naeem — Mon, 25 Mar 2013 06:12:54 GMT

hi,

i am working on c64. i want to ask a few questions

1- i want to preform upsampling and downsampling on some data. Is there any library function provided by ti that implements polyphase filters ???

2- does the library functions (e.g. dsp_fir|_gen) use circular buffers??? if no, then are there any library functions that make use of circular buffers???

plz help!!!