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IPCGR atomicity

Hi,

We are using the IPCGR register to mange inter cores communications on a C6472.

At low data rate, the code works fine and we are able to synchronize the cores and send messages between them: The source core(s) set the IPCGR register of the destination core, and wait for the destination core to clear it before sending a new message.

However, when we push the data rate up and/or multiple cores start sending message to a single destination core, we starts loosing messages!!!

Currently we think that the problem is the atomicity of the IPCGR register. In our case we think that the command below is not atomic (core 1 reads the IPCGR, core 2 reads the IPCGR, core 1 write it back, core 2 OVERWRITE it, and we loose the message from core1):

                                                       ipcRegs_p->IPCGR[dstID]  |=  (1 << (DNUM + 1)) | 1;   //write the source core ID bit and trigger interrupt

                                                                                                                                                       //where (1 << (DNUM + 1)) is the source core ID bit

All documents indicates that IPCGR register access are atomic. But in our case, we are reading, Oring, then writting back.

So my question:

is Reading, Oring, then Writting back is a single atomic instruction?

if not, should we use something like LL, SL, and CMTL?

thanks

khaled.

  • khaled,

    khaled saab said:
    All documents indicates that IPCGR register access are atomic.

    Where do you find this statement in which documents? The description of the IPCGRn registers in the datasheet made no mention of "atomic". These registers are better than atomic. For the source core to generate an interrupt, you do not read them you only write to the IPCGRn registers.

    You tagged your post with the TCI6486. If that is the device you are using, you may want to contact your sales and support channel for advice.

    khaled saab said:

    is Reading, Oring, then Writting back is a single atomic instruction?

    No. You can take a look at the assembly code generated by the compiler. Even without knowing your compiler options, I can tell you it is not atomic. It is not intended to be atomic, though.

    khaled saab said:

    if not, should we use something like LL, SL, and CMTL?

    No. The datasheet details how the registers are used for both reads and writes. Your code may have been written based on some other documents with which I am not familiar.

    A good choice would be to use or study the IPC module from the MCSDK package that is available by searching the TI Wiki Pages.

    Also, you can take a look at a CCSv4 project I posted on another thread, here. This does not use the MCSDK's IPC module.

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

  • Thanks, that was very helpful.

    we found the problem. After re-reading the documentation, we found that writting "0"'s to the IPCGR register has no effect and thus we don't have to read the IPCGR register and modify it. Thus, we don't have to read back and Or the IPCGR register. All what we have to do is to write the bits  that are of interest without worrying about messing the other bits.

    khaled.