Hi,
We are using the IPCGR register to mange inter cores communications on a C6472.
At low data rate, the code works fine and we are able to synchronize the cores and send messages between them: The source core(s) set the IPCGR register of the destination core, and wait for the destination core to clear it before sending a new message.
However, when we push the data rate up and/or multiple cores start sending message to a single destination core, we starts loosing messages!!!
Currently we think that the problem is the atomicity of the IPCGR register. In our case we think that the command below is not atomic (core 1 reads the IPCGR, core 2 reads the IPCGR, core 1 write it back, core 2 OVERWRITE it, and we loose the message from core1):
ipcRegs_p->IPCGR[dstID] |= (1 << (DNUM + 1)) | 1; //write the source core ID bit and trigger interrupt
//where (1 << (DNUM + 1)) is the source core ID bit
All documents indicates that IPCGR register access are atomic. But in our case, we are reading, Oring, then writting back.
So my question:
is Reading, Oring, then Writting back is a single atomic instruction?
if not, should we use something like LL, SL, and CMTL?
thanks
khaled.