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C6474 external mem (DDR) sync under CCS3.3 simulator

HRi
Guru 10750 points

Hi all,

Is there a way to sync the external mem (DDR) between the 3 C6474 cores under CCS3.3 simulator?

Thanks,

Haim

  • 0
    TI__Intellectual 1380 points

    Hi Haim,

     

    Can you detail the meaning of 'Sync'?

     

    REgards,

    Nizam

     

  • 0 in reply to Nizamudheen A
    Guru 10750 points

    Hi Nizam,

    The DDR2 should be R/W from the same address by the 3 cores (0x80000000) but what happen is that if I'm writing to the DDR at address x by core 0 I'm getting different data at address x from core 1 or 2 where it should be the same data,

    Please let me know if additional info is needed,

    Many Thanks,

    Haim

  • 0 in reply to HRi
    TI__Mastermind 18130 points

    I do not think that the simulator is capable of updating the 'DDR' seen from other simulators automatically, but maybe one of the simulator guys can chime in here.

  • 0 in reply to HRi
    TI__Intellectual 1380 points

    Hi Haim,

     

    You seem to notice data incoherencey across different cores, for the same memory location of DDR2.

    This may happen because of the caches in the system. You might notice that a given address 'x' is cached in each Core's (memory-system's) L1/L2 cache. In such a state, updates to the address 'x' by a given core is updated  locally to the cache'ed value, than the DDR value. Unless the cache contents are fluxhed to DDR2 memory, other core may read a stale data to address 'x'. 

    Hope this helps. LMK if you need more details on flushing the cache and so on.

     

    Regards,

    Nizam

     

  • 0 in reply to Nizamudheen A
    TI__Mastermind 18130 points

    Nizam,

    That is a good thought, but Haim mentioned he was using the simulator and not an actual target. The issue here is that you have three simulated cores running in three different instances of CCS via Parallel Debug Manager. Is there anyway to sync up the contents of "DDR" located at 0x80000000 between each of these three cores in the simulator? I am assuming this is not doable, but hoping for expert feedback [:)]

  • 0 in reply to Nizamudheen A
    Guru 10750 points

    Hi Nizam,

    You are correct without using the L2 cache the issue is solved (I didn't checked this yet with the simulator) but as I want to use the cache can you please let me know where I can find more info regarding the cache handling,

    Many Thanks,

    Haim

  • 0 in reply to HRi
    TI__Mastermind 18130 points

    I am glad I was wrong here!

    Regarding cache handling there are several articles on the Embedded Processors Wiki that may help including:

    - Cache Management
    - Enabling Cache on C64x+

    But you may also want to view the document on the cache for your specific device as this sometimes contains device-specific information as well.

  • 0 in reply to TimHarron
    Guru 10750 points

    Tim,

    Thank you very much,

    Haim