Clock Requirement of the board is as mentioned below.

I would like to know whether the clock source which I want to use it for SYSLK ,is it possible to use for SERDES clock(SRIO) by using a synthesizer and jitter cleaner.( for eg:CDCE 706 is having 6 programmmable port.ONE port we can use it for SYSCLK , 61.42MHz and One port for SERDES Clock, 125Mhz controlled by using I2C).In EVM module, it is using seperate 125MHz crystal for doing the same.

Please kindly suggest.

Thanks and regards,

Vedananda gowd.R

CLOCK REQUIREMENT

TMS 320C6474(Requirement is for 8 DSP Processors)

SYSCLK - 61.44 MHz - 2 PS RMS

DDRCLK - 66.0MHz - 30 PS RMS

SRIO/EMAC - 125 MHz - 4 PS RMS

FRAMESYNC - 30.72 MHz - 800PS RMS (SHOULD BE DERIVED FROM BUFFER WHICH GIVES SYSCLK)

IDT CHIP

S_CLK - 156.25 MHz - 3PS RMS

P_CLK - 100MHz - 300PS PP

CONTROLER

XIN - 12MHz - NO JITTER SPEC

XIN32 - 32.684KHz - NO JITTER SPEC

FPGA

XCLK ( FRAMESYNC) - 30.72 MHz - 800PS RMS (SHOULD BE DERIVED FROM BUFFER WHICH GIVES SYSCLK)

XCLK1 - 25MHz(FROM BACKPLANE REFERANCE CLK)

ETHERNET CONTROLLER

XIN - 25MHz