Hi, all!
When using C6474 simulator to simulate one program, from the datasheet, it seems that any core can access any memory on-chip through the global memory map! The problem is when core 0 tried to access the L1D sram in core1 ( which is configured as L1d sram, not cache), the simulator terminated because of serious error!
As all the on-chip memory has its unique global address, so it should be accessed directly by any DSP core, is that right? What caused the CCS simulator to be terminated then?
Thanks all!
touse