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C6000 Multicore DSP
C64x Multicore DSP Forum
C6474 I2C master boot unstable occasionally
Hello, I have used C6474 I2C master boot for a long time, but sometimes I find it doesnot work , such as the flashing leds which should flash after boot do not flash.This case doesn't always happen, but the boot mechanism is very critical for our application, whenever it reappears, simply POR for DSP for another new boot doesn't improve the case, unless power failure. so we have to restart our tester, otherwize we can do nothing.
In my param config table, I use I2C boot at 100kHz. the param tables are mainly used for config phy (88e6122),ddr2 and change to emac boot when device number equals 1, and for secondary bootloader from SPI flash when device number equals 0.
The boot fails more in the latter situation ,but the former exists failure too. we now mainly adopt the former situation ,namely first I2C boot and then switch to emac boot mode. it sometimes cannot boot DSP, because we donnot receive any signal DSP sends as soon as it boots successfully. Can we say that the inital code is not loaded successfully , so phy is not configed correctly.
I am very confused, does anyone have encounter the same or similar circumstance and how do you slove the problem? do I have some carelessnesses when I design the boot mechanism? or does it really exist that C6474 I2C eeprom boot do not work on a low probality?
Hope your help or suggestion!
thank you, Best regards.
We are also facing the same issue. Is this issue got solved? if so, how did you solve the issue?.
It is not simple to examine your board issue remotely, as you understand. If there was any problem with reliability of the I2C boot mode, it would be mentioned in the C6474 errata document which you have checked. Otherwise, i2C boot mode is well-known to be reliable as described in the datasheet and the bootloader User's Guide or Application Note.
Because your problems are not solved by asserting POR, my suspicion is that some part of the power sequencing order and timing as well as the clock and reset timing does not meet the device requirements. Please measure and verify these against the guidelines in the C6474 datasheet. My assumption is that this is being done on a custom board.
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We are still faced with the I2C boot fail issue now. It just doesn't work in a little chance, but I have to find the reason.
There are 3 TMS320C6474 DSPs on our custom board, and a Xilinx FPGA is used to control the reset and boot configuration logic of DSPs.
Whenever the board is powered-up, FPGA configure the device number of I2C eeprom to 1, then POR the 3 DSPs for a new boot, all of them excute from the boot ROM to read the respecific eeprom...
sometimes I find one of the DSP doesn't boot succsessfully, then I connect CCS3.3, view memory and registers, as for the DSP which has encountered an error condition, its I2C interface registers configuration is obviously different from the others which boot ok (why is it?), and certainly some flags I have written among the eeprom code are not set too.
then I POR the DSPs through FPGA, let them reboot . but the DSP which has boot failed still doesn't work., the error information is the same with before. I use an I2C test program to read eeprom in an emulation situtation, the result is that eeprom read operaion fails too. Can I judge that in this case, the DSP cannot read eeprom from the board power-up for some reasons?
SO I have to power down the board, and then power up, For most cases, the 3 DSPs all will boot successfully.
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