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Digital Signal Processors (DSP)
C6000 Multicore DSP
C64x Multicore DSP Forum
VCP2 sharing in multicore processor TI's 6487
I want to build an application to share VCP2 across 3 cores of TCI6487 Device. EDMA3 will be used for the VCP2 communication. I am planning to use the concept of Hardware Semaphores in combined mode (that is direct and indirect) for VCP2 sharing between 3 cores. For example it will work as follows:
1. Init VCP2
2. Check the status of VCP2 (using hardware sem), to see if it is free or not. If not, wait till it's free
3. When free, configure and trigger the EDMA3
4. Wait for the completion interrupt from EDMA3
5. Release the VCP2 for other cores
Core 1 and 2:
1. Check the status of VCP2 (using hardware sem), to see if it is free or not. If not, wait till it's free
2. When free, configure and trigger the EDMA3
3. Wait for the completion interrupt from EDMA3
4. Release the VCP2 for other cores
Is this the correct way of using HW Semaphore for VCP2 sharing between 3 cores?
The only problem I see here is that EDMA3 has got 2 channels 28 and 29 for TX and RX respectively and I am planning to use the global region for EDMA3. Since I am going to use EDMA3, is it possible to use only these 2 channels in the global region for all the 3 cores? or I have to configure these channels in different regions in the above approach?
Please provide me the inputs for the above approach.
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