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SRIO Illegal Transaction Decode Error

Nick Borton
Genius 3595 points

Hello,


I've been attempting to send messages from an FPGA to a C6472. I had it close to working a couple of weeks ago, and I've been trying to get the last piece of info for this thread: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/t/351156.aspx

But I have been getting Illegal Transaction Decode errors in the ERR_DET register.

Here is a register dump from CCS:

[0 ... 99]    
    PORT_OPTION_0_SP_RST_OPT    0x00000000    Port Reset Option CSR [Memory Mapped]    
    PORT_OPTION_0_SP_CTL_INDEP    0x21A201C0    Port Control Independent register [Memory Mapped]    
    PORT_OPTION_0_SP_SILENCE_TIMER    0x10000000    Port Silence Timer [Memory Mapped]    
    PORT_OPTION_0_SP_MULT_EVNT_CS    0x00000000    Port  Multicast-Event Control Symbol Request register [Memory Mapped]    
    PORT_OPTION_0_SP_CS_TX    0x40FC8000    Port  Control Symbol Transmit [Memory Mapped]    
    PORT_OPTION_1_SP_RST_OPT    0x00000000    Port Reset Option CSR [Memory Mapped]    
    PORT_OPTION_1_SP_CTL_INDEP    0x00000000    Port Control Independent register [Memory Mapped]    
    PORT_OPTION_1_SP_SILENCE_TIMER    0x00000000    Port Silence Timer [Memory Mapped]    
    PORT_OPTION_1_SP_MULT_EVNT_CS    0x00000000    Port  Multicast-Event Control Symbol Request register [Memory Mapped]    
    PORT_OPTION_1_SP_CS_TX    0x00000000    Port  Control Symbol Transmit [Memory Mapped]    
    PORT_OPTION_2_SP_RST_OPT    0x00000000    Port Reset Option CSR [Memory Mapped]    
    PORT_OPTION_2_SP_CTL_INDEP    0x00000000    Port Control Independent register [Memory Mapped]    
    PORT_OPTION_2_SP_SILENCE_TIMER    0x00000000    Port Silence Timer [Memory Mapped]    
    PORT_OPTION_2_SP_MULT_EVNT_CS    0x00000000    Port  Multicast-Event Control Symbol Request register [Memory Mapped]    
    PORT_OPTION_2_SP_CS_TX    0x00000000    Port  Control Symbol Transmit [Memory Mapped]    
    PORT_OPTION_3_SP_RST_OPT    0x00000000    Port Reset Option CSR [Memory Mapped]    
    PORT_OPTION_3_SP_CTL_INDEP    0x00000000    Port Control Independent register [Memory Mapped]    
    PORT_OPTION_3_SP_SILENCE_TIMER    0x00000000    Port Silence Timer [Memory Mapped]    
    PORT_OPTION_3_SP_MULT_EVNT_CS    0x00000000    Port  Multicast-Event Control Symbol Request register [Memory Mapped]    
    PORT_OPTION_3_SP_CS_TX    0x00000000    Port  Control Symbol Transmit [Memory Mapped]    
    PORT_ERROR_0_SP_ERR_DET    0x80100000    Port Error Detect CSR [Memory Mapped]    
    PORT_ERROR_0_SP_RATE_EN    0x807E0033    Port Error Enable CSR [Memory Mapped]    
    PORT_ERROR_0_SP_ERR_ATTR_CAPT_DBG0    0x00000000    Port Attributes Error Capture CSR  [Memory Mapped]    
    PORT_ERROR_0_SP_ERR_CAPT_DBG_0    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_0_SP_ERR_CAPT_DBG_1    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_0_SP_ERR_CAPT_DBG_2    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_0_SP_ERR_CAPT_DBG_3    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_0_SP_ERR_RATE    0x0F000404    Port  Error Rate CSR [Memory Mapped]    
    PORT_ERROR_0_SP_ERR_THRESH    0x0A0A0000    Port Error Rate Threshold CSR [Memory Mapped]    
    PORT_ERROR_1_SP_ERR_DET    0x00000000    Port Error Detect CSR [Memory Mapped]    
    PORT_ERROR_1_SP_RATE_EN    0x00000000    Port Error Enable CSR [Memory Mapped]    
    PORT_ERROR_1_SP_ERR_ATTR_CAPT_DBG0    0x00000000    Port Attributes Error Capture CSR  [Memory Mapped]    
    PORT_ERROR_1_SP_ERR_CAPT_DBG_0    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_1_SP_ERR_CAPT_DBG_1    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_1_SP_ERR_CAPT_DBG_2    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_1_SP_ERR_CAPT_DBG_3    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_1_SP_ERR_RATE    0x00000000    Port  Error Rate CSR [Memory Mapped]    
    PORT_ERROR_1_SP_ERR_THRESH    0x00000000    Port Error Rate Threshold CSR [Memory Mapped]    
    PORT_ERROR_2_SP_ERR_DET    0x00000000    Port Error Detect CSR [Memory Mapped]    
    PORT_ERROR_2_SP_RATE_EN    0x00000000    Port Error Enable CSR [Memory Mapped]    
    PORT_ERROR_2_SP_ERR_ATTR_CAPT_DBG0    0x00000000    Port Attributes Error Capture CSR  [Memory Mapped]    
    PORT_ERROR_2_SP_ERR_CAPT_DBG_0    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_2_SP_ERR_CAPT_DBG_1    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_2_SP_ERR_CAPT_DBG_2    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_2_SP_ERR_CAPT_DBG_3    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_2_SP_ERR_RATE    0x00000000    Port  Error Rate CSR [Memory Mapped]    
    PORT_ERROR_2_SP_ERR_THRESH    0x00000000    Port Error Rate Threshold CSR [Memory Mapped]    
    PORT_ERROR_3_SP_ERR_DET    0x00000000    Port Error Detect CSR [Memory Mapped]    
    PORT_ERROR_3_SP_RATE_EN    0x00000000    Port Error Enable CSR [Memory Mapped]    
    PORT_ERROR_3_SP_ERR_ATTR_CAPT_DBG0    0x00000000    Port Attributes Error Capture CSR  [Memory Mapped]    
    PORT_ERROR_3_SP_ERR_CAPT_DBG_0    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_3_SP_ERR_CAPT_DBG_1    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_3_SP_ERR_CAPT_DBG_2    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_3_SP_ERR_CAPT_DBG_3    0x00000000    Port Packet/Control Symbol Error Capture CSR [Memory Mapped]    
    PORT_ERROR_3_SP_ERR_RATE    0x00000000    Port  Error Rate CSR [Memory Mapped]    
    PORT_ERROR_3_SP_ERR_THRESH    0x00000000    Port Error Rate Threshold CSR [Memory Mapped]    
    PORT_0_SP_LM_REQ    0x00000000    Port  Link Maintenance Request CSR [Memory Mapped]    
    PORT_0_SP_LM_RESP    0x800003A5    Port  Link Maintenance Response CSR [Memory Mapped]    
    PORT_0_SP_ACKID_STAT    0x05000000    Port  Local AckID Status CSR [Memory Mapped]    
    PORT_0_SP_ERR_STAT    0x04010012    Port  Error and Status CSR [Memory Mapped]    
    PORT_0_SP_CTL    0x0068000D    Port  Control CSR [Memory Mapped]    
    PORT_1_SP_LM_REQ    0x00000000    Port  Link Maintenance Request CSR [Memory Mapped]    
    PORT_1_SP_LM_RESP    0x000003A5    Port  Link Maintenance Response CSR [Memory Mapped]    
    PORT_1_SP_ACKID_STAT    0x05000000    Port  Local AckID Status CSR [Memory Mapped]    
    PORT_1_SP_ERR_STAT    0x04010012    Port  Error and Status CSR [Memory Mapped]    
    PORT_1_SP_CTL    0x0068000D    Port  Control CSR [Memory Mapped]    
    PORT_2_SP_LM_REQ    0x00000000    Port  Link Maintenance Request CSR [Memory Mapped]    
    PORT_2_SP_LM_RESP    0x000003A5    Port  Link Maintenance Response CSR [Memory Mapped]    
    PORT_2_SP_ACKID_STAT    0x05000000    Port  Local AckID Status CSR [Memory Mapped]    
    PORT_2_SP_ERR_STAT    0x04010012    Port  Error and Status CSR [Memory Mapped]    
    PORT_2_SP_CTL    0x0068000D    Port  Control CSR [Memory Mapped]    
    PORT_3_SP_LM_REQ    0x00000000    Port  Link Maintenance Request CSR [Memory Mapped]    
    PORT_3_SP_LM_RESP    0x000003A5    Port  Link Maintenance Response CSR [Memory Mapped]    
    PORT_3_SP_ACKID_STAT    0x05000000    Port  Local AckID Status CSR [Memory Mapped]    
    PORT_3_SP_ERR_STAT    0x04010012    Port  Error and Status CSR [Memory Mapped]    
    PORT_3_SP_CTL    0x0068000D    Port  Control CSR [Memory Mapped]    
    MAP_0_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_0_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_1_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_1_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_2_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_2_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_3_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_3_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_4_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_4_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_5_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_5_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_6_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_6_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_7_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_7_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_8_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_8_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_9_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_9_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_10_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_10_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_11_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_11_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
[100 ... 199]    
    MAP_12_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_12_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_13_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_13_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_14_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_14_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_15_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_15_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_16_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_16_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_17_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_17_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_18_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_18_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_19_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_19_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_20_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_20_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_21_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_21_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_22_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_22_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_23_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_23_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_24_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_24_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_25_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_25_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_26_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_26_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_27_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_27_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_28_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_28_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_29_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_29_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_30_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_30_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_31_RXU_MAP_L    0x000000EE    MailBox-to-queue mapping register [Memory Mapped]    
    MAP_31_RXU_MAP_H    0x00000102    MailBox-to-queue mapping register [Memory Mapped]    
    BLK_ENABLE_0_BLK_EN    0x00000001    Block Enable [Memory Mapped]    
    BLK_ENABLE_0_BLK_EN_STAT    0x00000001    Block Enable Status [Memory Mapped]    
    BLK_ENABLE_1_BLK_EN    0x00000001    Block Enable [Memory Mapped]    
    BLK_ENABLE_1_BLK_EN_STAT    0x00000001    Block Enable Status [Memory Mapped]    
    BLK_ENABLE_2_BLK_EN    0x00000001    Block Enable [Memory Mapped]    
    BLK_ENABLE_2_BLK_EN_STAT    0x00000001    Block Enable Status [Memory Mapped]    
    BLK_ENABLE_3_BLK_EN    0x00000001    Block Enable [Memory Mapped]    
    BLK_ENABLE_3_BLK_EN_STAT    0x00000001    Block Enable Status [Memory Mapped]    
    BLK_ENABLE_4_BLK_EN    0x00000001    Block Enable [Memory Mapped]    
    BLK_ENABLE_4_BLK_EN_STAT    0x00000001    Block Enable Status [Memory Mapped]    
    BLK_ENABLE_5_BLK_EN    0x00000001    Block Enable [Memory Mapped]    
    BLK_ENABLE_5_BLK_EN_STAT    0x00000001    Block Enable Status [Memory Mapped]    
    BLK_ENABLE_6_BLK_EN    0x00000001    Block Enable [Memory Mapped]    
    BLK_ENABLE_6_BLK_EN_STAT    0x00000001    Block Enable Status [Memory Mapped]    
    BLK_ENABLE_7_BLK_EN    0x00000001    Block Enable [Memory Mapped]    
    BLK_ENABLE_7_BLK_EN_STAT    0x00000001    Block Enable Status [Memory Mapped]    
    BLK_ENABLE_8_BLK_EN    0x00000001    Block Enable [Memory Mapped]    
    BLK_ENABLE_8_BLK_EN_STAT    0x00000001    Block Enable Status [Memory Mapped]    
    LSU_0_LSU_REG0    0x00000000    LSU Control register0 [Memory Mapped]    
    LSU_0_LSU_REG1    0x00000000    LSU Control register1 [Memory Mapped]    
    LSU_0_LSU_REG2    0x00000000    LSU Control register2 [Memory Mapped]    
    LSU_0_LSU_REG3    0x00000000    LSU Control register3 [Memory Mapped]    
    LSU_0_LSU_REG4    0x00000000    LSU Control register4 [Memory Mapped]    
    LSU_0_LSU_REG5    0x00000000    LSU Control register5 [Memory Mapped]    
    LSU_0_LSU_REG6    0x00000000    LSU Control register6 [Memory Mapped]    
    LSU_0_LSU_FLOW_MASKS    0x0000FFFF    Core n LSU Congestion Control Flow Mask [Memory Mapped]    
    LSU_1_LSU_REG0    0x00000000    LSU Control register0 [Memory Mapped]    
    LSU_1_LSU_REG1    0x00000000    LSU Control register1 [Memory Mapped]    
    LSU_1_LSU_REG2    0x00000000    LSU Control register2 [Memory Mapped]    
    LSU_1_LSU_REG3    0x00000000    LSU Control register3 [Memory Mapped]    
    LSU_1_LSU_REG4    0x00000000    LSU Control register4 [Memory Mapped]    
    LSU_1_LSU_REG5    0x00000000    LSU Control register5 [Memory Mapped]    
    LSU_1_LSU_REG6    0x00000000    LSU Control register6 [Memory Mapped]    
    LSU_1_LSU_FLOW_MASKS    0x0000FFFF    Core n LSU Congestion Control Flow Mask [Memory Mapped]    
    LSU_2_LSU_REG0    0x00000000    LSU Control register0 [Memory Mapped]    
    LSU_2_LSU_REG1    0x00000000    LSU Control register1 [Memory Mapped]    
    LSU_2_LSU_REG2    0x00000000    LSU Control register2 [Memory Mapped]    
    LSU_2_LSU_REG3    0x00000000    LSU Control register3 [Memory Mapped]    
    LSU_2_LSU_REG4    0x00000000    LSU Control register4 [Memory Mapped]    
    LSU_2_LSU_REG5    0x00000000    LSU Control register5 [Memory Mapped]    
    LSU_2_LSU_REG6    0x00000000    LSU Control register6 [Memory Mapped]    
    LSU_2_LSU_FLOW_MASKS    0x0000FFFF    Core n LSU Congestion Control Flow Mask [Memory Mapped]    
    LSU_3_LSU_REG0    0x00000000    LSU Control register0 [Memory Mapped]    
    LSU_3_LSU_REG1    0x00000000    LSU Control register1 [Memory Mapped]    
    LSU_3_LSU_REG2    0x00000000    LSU Control register2 [Memory Mapped]    
    LSU_3_LSU_REG3    0x00000000    LSU Control register3 [Memory Mapped]    
    LSU_3_LSU_REG4    0x00000000    LSU Control register4 [Memory Mapped]    
    LSU_3_LSU_REG5    0x00000000    LSU Control register5 [Memory Mapped]    
    LSU_3_LSU_REG6    0x00000000    LSU Control register6 [Memory Mapped]    
    LSU_3_LSU_FLOW_MASKS    0x0000FFFF    Core n LSU Congestion Control Flow Mask [Memory Mapped]    
    DOORBELL_INTR_0_DOORBELL_ICSR    0x00000000    DOORBELL Interrupt Status register [Memory Mapped]    
    DOORBELL_INTR_0_DOORBELL_ICCR    0x00000000    DOORBELL Interrupt Clear register [Memory Mapped]    
    DOORBELL_INTR_1_DOORBELL_ICSR    0x00000000    DOORBELL Interrupt Status register [Memory Mapped]    
    DOORBELL_INTR_1_DOORBELL_ICCR    0x00000000    DOORBELL Interrupt Clear register [Memory Mapped]    
    DOORBELL_INTR_2_DOORBELL_ICSR    0x00000000    DOORBELL Interrupt Status register [Memory Mapped]    
    DOORBELL_INTR_2_DOORBELL_ICCR    0x00000000    DOORBELL Interrupt Clear register [Memory Mapped]    
    DOORBELL_INTR_3_DOORBELL_ICSR    0x00000000    DOORBELL Interrupt Status register [Memory Mapped]    
    DOORBELL_INTR_3_DOORBELL_ICCR    0x00000000    DOORBELL Interrupt Clear register [Memory Mapped]    
    DOORBELL_INTR_ROUTE_0_DOORBELL_ICRR    0x00000000    DOORBELL Interrupt Condition Routing register (0 to 7) [Memory Mapped]    
    DOORBELL_INTR_ROUTE_0_DOORBELL_ICRR2    0x00000000    DOORBELL Interrupt Condition Routing register (8 to 15) [Memory Mapped]    
[200 ... 299]    
    DOORBELL_INTR_ROUTE_1_DOORBELL_ICRR    0x00000000    DOORBELL Interrupt Condition Routing register (0 to 7) [Memory Mapped]    
    DOORBELL_INTR_ROUTE_1_DOORBELL_ICRR2    0x00000000    DOORBELL Interrupt Condition Routing register (8 to 15) [Memory Mapped]    
    DOORBELL_INTR_ROUTE_2_DOORBELL_ICRR    0x00000000    DOORBELL Interrupt Condition Routing register (0 to 7) [Memory Mapped]    
    DOORBELL_INTR_ROUTE_2_DOORBELL_ICRR2    0x00000000    DOORBELL Interrupt Condition Routing register (8 to 15) [Memory Mapped]    
    DOORBELL_INTR_ROUTE_3_DOORBELL_ICRR    0x00000000    DOORBELL Interrupt Condition Routing register (0 to 7) [Memory Mapped]    
    DOORBELL_INTR_ROUTE_3_DOORBELL_ICRR2    0x00000000    DOORBELL Interrupt Condition Routing register (8 to 15) [Memory Mapped]    
    HW_PKT_FWD_0_PF_16BIT_CNTL    0xFFFFFFFF    Packet Forwarding register for 16b DeviceIDs [Memory Mapped]    
    HW_PKT_FWD_0_PF_8BIT_CNTL    0x0003FFFF    Packet Forwarding register for 8b DeviceIDs [Memory Mapped]    
    HW_PKT_FWD_1_PF_16BIT_CNTL    0xFFFFFFFF    Packet Forwarding register for 16b DeviceIDs [Memory Mapped]    
    HW_PKT_FWD_1_PF_8BIT_CNTL    0x0003FFFF    Packet Forwarding register for 8b DeviceIDs [Memory Mapped]    
    HW_PKT_FWD_2_PF_16BIT_CNTL    0xFFFFFFFF    Packet Forwarding register for 16b DeviceIDs [Memory Mapped]    
    HW_PKT_FWD_2_PF_8BIT_CNTL    0x0003FFFF    Packet Forwarding register for 8b DeviceIDs [Memory Mapped]    
    HW_PKT_FWD_3_PF_16BIT_CNTL    0xFFFFFFFF    Packet Forwarding register for 16b DeviceIDs [Memory Mapped]    
    HW_PKT_FWD_3_PF_8BIT_CNTL    0x0003FFFF    Packet Forwarding register for 8b DeviceIDs [Memory Mapped]    
    PID    0x44A23102    Peripheral Identification Register [Memory Mapped]    
    PCR    0x00000005    Peripheral Control register [Memory Mapped]    
    PER_SET_CNTL    0x0D400360    Peripheral  Settings Control register [Memory Mapped]    
    GBL_EN    0x00000001    Peripheral Global Enable register [Memory Mapped]    
    GBL_EN_STAT    0x00000073    Peripheral Global Enable Status [Memory Mapped]    
    DEVICEID_REG1    0x00FF00FF    RapidIO DEVICEID1 Register [Memory Mapped]    
    DEVICEID_REG2    0x00FF00FF    RapidIO DEVICEID2 Register [Memory Mapped]    
    SERDES_CFGRX_CNTL_0    0x00081101    SerDes RX Channels CFG register [Memory Mapped]    
    SERDES_CFGRX_CNTL_1    0x00081101    SerDes RX Channels CFG register [Memory Mapped]    
    SERDES_CFGRX_CNTL_2    0x00000000    SerDes RX Channels CFG register [Memory Mapped]    
    SERDES_CFGRX_CNTL_3    0x00000000    SerDes RX Channels CFG register [Memory Mapped]    
    SERDES_CFGTX_CNTL_0    0x00000401    SerDes TX Channels CFG register [Memory Mapped]    
    SERDES_CFGTX_CNTL_1    0x00000400    SerDes TX Channels CFG register [Memory Mapped]    
    SERDES_CFGTX_CNTL_2    0x00000000    SerDes TX Channels CFG register [Memory Mapped]    
    SERDES_CFGTX_CNTL_3    0x00000000    SerDes TX Channels CFG register [Memory Mapped]    
    SERDES_CFG_CNTL_0    0x0000000F    SerDes  Macros CFG register [Memory Mapped]    
    SERDES_CFG_CNTL_1    0x00000000    SerDes  Macros CFG register [Memory Mapped]    
    SERDES_CFG_CNTL_2    0x00000000    SerDes  Macros CFG register [Memory Mapped]    
    SERDES_CFG_CNTL_3    0x00000000    SerDes  Macros CFG register [Memory Mapped]    
    RX_CPPI_ICSR    0x00000000    RX CPPI Interrupt Status register [Memory Mapped]    
    RX_CPPI_ICCR    0x00000000    RX CPPI Interrupt Clear register [Memory Mapped]    
    TX_CPPI_ICSR    0x00000000    TX CPPI Interrupt Status register [Memory Mapped]    
    TX_CPPI_ICCR    0x00000000    TX CPPI Interrupt Clear register [Memory Mapped]    
    LSU_ICSR    0x00000000    LSU Status Interrupt register [Memory Mapped]    
    LSU_ICCR    0x00000000    LSU Clear Interrupt register [Memory Mapped]    
    ERR_RST_EVNT_ICSR    0x00000004    Error, Reset, and Special Event Status Interrupt register [Memory Mapped]    
    ERR_RST_EVNT_ICCR    0x00000000    Error, Reset, and Special Event Clear Interrupt register [Memory Mapped]    
    RX_CPPI_ICRR    0x00000000    RX CPPI Interrupt Condition Routing register (0 to 7) [Memory Mapped]    
    RX_CPPI_ICRR2    0x00000000    RX CPPI Interrupt Condition Routing register (8 to 15) [Memory Mapped]    
    TX_CPPI_ICRR    0x00000000    TX CPPI Interrupt Condition Routing register (0 to 7) [Memory Mapped]    
    TX_CPPI_ICRR2    0x00000000    TX CPPI Interrupt Condition Routing register (8 to 15) [Memory Mapped]    
    LSU_ICRR_0    0x00000000    LSU Module Interrupt Condition Routing register [Memory Mapped]    
    LSU_ICRR_1    0x00000000    LSU Module Interrupt Condition Routing register [Memory Mapped]    
    LSU_ICRR_2    0x00000000    LSU Module Interrupt Condition Routing register [Memory Mapped]    
    LSU_ICRR_3    0x00000000    LSU Module Interrupt Condition Routing register [Memory Mapped]    
    ERR_RST_EVNT_ICRR    0x00000000    Err/Reset/special event Interrupt Condition Routing register [Memory Mapped]    
    ERR_RST_EVNT_ICRR2    0x00000000    Err/Reset/special event Interrupt Condition Routing register [Memory Mapped]    
    ERR_RST_EVNT_ICRR3    0x00000000    Err/Reset/special event Interrupt Condition Routing register [Memory Mapped]    
    INTDST_DECODE_0    0x40000000    INTDST Interrupt Status Decode registers [Memory Mapped]    
    INTDST_DECODE_1    0x00000000    INTDST Interrupt Status Decode registers [Memory Mapped]    
    INTDST_DECODE_2    0x00000000    INTDST Interrupt Status Decode registers [Memory Mapped]    
    INTDST_DECODE_3    0x00000000    INTDST Interrupt Status Decode registers [Memory Mapped]    
    INTDST_DECODE_4    0x00000000    INTDST Interrupt Status Decode registers [Memory Mapped]    
    INTDST_DECODE_5    0x00000000    INTDST Interrupt Status Decode registers [Memory Mapped]    
    INTDST_DECODE_6    0x00000000    INTDST Interrupt Status Decode registers [Memory Mapped]    
    INTDST_DECODE_7    0x00000000    INTDST Interrupt Status Decode registers [Memory Mapped]    
    INTDST_RATE_CNTL_0    0x00000001    INTDST Interrupt Rate Control registers [Memory Mapped]    
    INTDST_RATE_CNTL_1    0x00000000    INTDST Interrupt Rate Control registers [Memory Mapped]    
    INTDST_RATE_CNTL_2    0x00000000    INTDST Interrupt Rate Control registers [Memory Mapped]    
    INTDST_RATE_CNTL_3    0x00000000    INTDST Interrupt Rate Control registers [Memory Mapped]    
    INTDST_RATE_CNTL_4    0x00000000    INTDST Interrupt Rate Control registers [Memory Mapped]    
    INTDST_RATE_CNTL_5    0x00000000    INTDST Interrupt Rate Control registers [Memory Mapped]    
    INTDST_RATE_CNTL_6    0x00000000    INTDST Interrupt Rate Control registers [Memory Mapped]    
    INTDST_RATE_CNTL_7    0x00000000    INTDST Interrupt Rate Control registers [Memory Mapped]    
    QUEUE_TXDMA_HDP_0    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_1    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_2    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_3    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_4    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_5    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_6    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_7    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_8    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_9    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_10    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_11    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_12    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_13    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_14    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_HDP_15    0x00000000    Queue TX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_0    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_1    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_2    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_3    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_4    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_5    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_6    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_7    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_8    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_9    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_10    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_11    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_12    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_13    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_14    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
    QUEUE_TXDMA_CP_15    0x00000000    Queue TX DMA Completion Pointer [Memory Mapped]    
[300 ... 394]    
    QUEUE_RXDMA_HDP_0    0x02E00000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_1    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_2    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_3    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_4    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_5    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_6    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_7    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_8    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_9    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_10    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_11    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_12    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_13    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_14    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_HDP_15    0x00000000    Queue RX DMA Head Descriptor Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_0    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_1    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_2    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_3    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_4    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_5    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_6    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_7    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_8    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_9    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_10    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_11    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_12    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_13    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_14    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    QUEUE_RXDMA_CP_15    0x00000000    Queue RX DMA Completion Pointer [Memory Mapped]    
    TX_QUEUE_TEAR_DOWN    0x00000000    TX Queue Tear-down Register [Memory Mapped]    
    TX_CPPI_FLOW_MASKS_0    0xFFFFFFFF    TX CPPI Supported Flow Mask [Memory Mapped]    
    TX_CPPI_FLOW_MASKS_1    0xFFFFFFFF    TX CPPI Supported Flow Mask [Memory Mapped]    
    TX_CPPI_FLOW_MASKS_2    0xFFFFFFFF    TX CPPI Supported Flow Mask [Memory Mapped]    
    TX_CPPI_FLOW_MASKS_3    0xFFFFFFFF    TX CPPI Supported Flow Mask [Memory Mapped]    
    TX_CPPI_FLOW_MASKS_4    0xFFFFFFFF    TX CPPI Supported Flow Mask [Memory Mapped]    
    TX_CPPI_FLOW_MASKS_5    0xFFFFFFFF    TX CPPI Supported Flow Mask [Memory Mapped]    
    TX_CPPI_FLOW_MASKS_6    0xFFFFFFFF    TX CPPI Supported Flow Mask [Memory Mapped]    
    TX_CPPI_FLOW_MASKS_7    0xFFFFFFFF    TX CPPI Supported Flow Mask [Memory Mapped]    
    RX_QUEUE_TEAR_DOWN    0x00000000    RX Queue Tear-down Register [Memory Mapped]    
    RX_CPPI_CNTL    0x00000000    RX CPPI Control register [Memory Mapped]    
    TX_QUEUE_CNTL0    0x03020100    TX CPPI Weighted Round Robin Control [Memory Mapped]    
    TX_QUEUE_CNTL1    0x07060504    TX CPPI Weighted Round Robin Control [Memory Mapped]    
    TX_QUEUE_CNTL2    0x0B0A0908    TX CPPI Weighted Round Robin Control [Memory Mapped]    
    TX_QUEUE_CNTL3    0x0F0E0D0C    TX CPPI Weighted Round Robin Control [Memory Mapped]    
    FLOW_CNTL_0    0x000100FF    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_1    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_2    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_3    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_4    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_5    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_6    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_7    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_8    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_9    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_10    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_11    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_12    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_13    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_14    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    FLOW_CNTL_15    0x00010000    Flow Control Table Entry Registers [Memory Mapped]    
    DEV_ID    0x00000030    Device Identity CAR [Memory Mapped]    
    DEV_INFO    0x00000000    Device Information CAR [Memory Mapped]    
    ASBLY_ID    0x00000030    Assembly Identity CAR  [Memory Mapped]    
    ASBLY_INFO    0x00000100    Assembly Information CAR [Memory Mapped]    
    PE_FEAT    0x20000019    Processing Element Features CAR [Memory Mapped]    
    SRC_OP    0x0000FDF4    Source Operations CAR [Memory Mapped]    
    DEST_OP    0x0000FC04    Destination Operations CAR [Memory Mapped]    
    PE_LL_CTL    0x00000000    Processing Element Logical Layer Control CSR [Memory Mapped]    
    LCL_CFG_HBAR    0x00000000    Local Configuration Space Base Address 0 CSR [Memory Mapped]    
    LCL_CFG_BAR    0x005A0200    Local Configuration Space Base Address 1 CSR [Memory Mapped]    
    BASE_ID    0x00FF00FF    Base Device ID CSR [Memory Mapped]    
    HOST_BASE_ID_LOCK    0x0000FFFF    Host Base Device ID Lock CSR [Memory Mapped]    
    COMP_TAG    0x00000000    Component Tag CSR [Memory Mapped]    
    SP_MB_HEAD    0x10000001    1x/4x LP-Serial Port Maintenance Block Header [Memory Mapped]    
    SP_LT_CTL    0x00FFFF00    Port Link Time-Out Control CSR [Memory Mapped]    
    SP_RT_CTL    0x00FFFF00    Port Response Time-Out Control CSR [Memory Mapped]    
    SP_GEN_CTL    0xC0000000    Port General Control CSR [Memory Mapped]    
    ERR_RPT_BH    0x00000007    Error Reporting Block Header [Memory Mapped]    
    ERR_DET    0x08000000    Logical/Transport Layer Error Detect CSR [Memory Mapped]    
    ERR_EN    0x8DC000C0    Logical/Transport Layer Error Enable CSR [Memory Mapped]    
    H_ADDR_CAPT    0x00000000    Logical/Transport Layer High Address Capture CSR [Memory Mapped]    
    ADDR_CAPT    0x00000000    Logical/Transport Layer Address Capture CSR [Memory Mapped]    
    ID_CAPT    0x00FF00EE    Logical/Transport Layer Device ID  Capture CSR [Memory Mapped]    
    CTRL_CAPT    0xB0000000    Logical/Transport Layer Control Capture CSR [Memory Mapped]    
    PW_TGT_ID    0x00000000    Port-Write Target Device ID CSR [Memory Mapped]    
    SP_IP_DISCOVERY_TIMER    0x90800000    Port IP Discovery Timer in 4x mode [Memory Mapped]    
    SP_IP_MODE    0x4000002A    Port IP Mode CSR [Memory Mapped]    
    IP_PRESCAL    0x00000021    Serial Port IP Prescalar [Memory Mapped]    
    SP_IP_PW_IN_CAPT_0    0x00000000    Port-Write-In Capture CSR [Memory Mapped]    
    SP_IP_PW_IN_CAPT_1    0x00000000    Port-Write-In Capture CSR [Memory Mapped]    
    SP_IP_PW_IN_CAPT_2    0x00000000    Port-Write-In Capture CSR [Memory Mapped]    
    SP_IP_PW_IN_CAPT_3    0x00000000    Port-Write-In Capture CSR [Memory Mapped]    

I'm at a bit of a loss as to why messages are no longer getting into the part. The Dev ID and Logical / Transport capture registers look OK to me for a message packet (Type 11)

Thanks!

  • 0
    Genius 3595 points

    I'm continuing to scrub through this. It happens on multiple systems.

    I've noticed that Port 0 SP_ERR_STAT is indicating that it thinks that the SW needs to initiate a port-write packet. Is that due to the other error? Port 0 has no indication of any other errors. And when that bit is set, it doesn't trigger an interrupt to cause the CPU to think it needs to issue a port-write.

    I'm also not seeing any input or output stop conditions, so my implementation of appendix B of the SRIO user guide is not coming into play.

    I'm still very confused.

  • 0 in reply to Nick Borton
    Genius 3595 points

    I have also noticed that the SRIO register display for the map registers just displays map 0 for every one.

    Here is the memory dump of the first few:

    000000EE    00000102    0000BEEF    00000107
    0000BEEF    0000010B    0000BEEF    0000010F
    0000BEEF    00000113    FF000000    00000100
    FF000000    00000100    FF000000    00000100
    FF000000    00000100    FF000000    00000100
    FF000000    00000100    FF000000    00000100
    FF000000    00000100    FF000000    00000100
    FF000000    00000100    FF000000    00000100
    FF000000    00000100    FF000000    00000100
    FF000000    00000100    FF000000    00000100
    FF000000    00000100    FF000000    00000100
    FF000000    00000100    FF000000    00000100
    FF000000    00000100    FF000000    00000100
    FF000000    00000100    FF000000    00000100

    I am intentionally setting up 5 maps. All of them should be promiscuous, map 0 is a single segment, and map 1-4 are multi segment maps. those five should be open to all mailboxes, letters and segments. They should respectively map to queues 0 through 4. Currently I am only assigning descriptors to queue 0, and I am sending a message less than 256 bytes long.

    The unused mappers seem to be initialized to only accept letter 0 on mailbox 0, and only accept messages from DEV ID 0 and send them to queue 0. I don't think this should be a problem.

    Is there any other initialization I should perform on these un-used mappers?

  • 0 in reply to Nick Borton
    Genius 3595 points

    Another odd thing I have noticed is the HOST_BASE_ID_LOCK register is not the value I write to it. The Dev ID of the C6472 is 0x00FF, which is the value I write to the register. Bit it seems to always show up as 0xFFFF.

    Could that be a potential problem?

  • 0 in reply to Nick Borton
    Genius 3595 points

    I believe I have figured out my problem. It seems that the issue was on the FPGA end. I'm guessing that the size of the packet did not match the message length. Is there anyway to see that info?

  • 0 in reply to Nick Borton
    TI__Guru* 81335 points

    Hi Norton,

    This post will help other community members. Thank you for the update.