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c6474 fsync problem

Hi,can you tell me the relationship between compareValue offset and the corresponding  value in EGM_COMPARE Register.if  my delta value is -700 and pi value is 750,how to configure my fsync module? I use obsai 4x rate to communicate with fpga. thank you

// event gen 5
/** configure mask based trigger event to occur every 4 chips for EDMA x'fer (DSP ->
AIF outbound RAM) */
configMaskTrigger[14].timerUsed = CSL_FSYNC_RP3_TIMER;
configMaskTrigger[14].eventGenUsed = CSL_FSYNC_TRIGGER_GEN_5;
configMaskTrigger[14].mask.frameMask = 0;
configMaskTrigger[14].mask.slotMask = 0;
configMaskTrigger[14].mask.chipTerminalCountIndexMask = 0;
configMaskTrigger[14].mask.chipMask = 0x3;
configMaskTrigger[14].mask.sampleMask = 0xFF;
// lag of 8 chips between AIF write and EDMA read
configMaskTrigger[14].offset.slotOffset = 1;
configMaskTrigger[14].offset.chipTerminalCountIndex = 0;
configMaskTrigger[14].offset.chipOffset = 1;
configMaskTrigger[14].offset.sampleOffset = 0;
configMaskTrigger[14].compareValue.slotValue = 0;
configMaskTrigger[14].compareValue.chipValue = 9;
configMaskTrigger[14].compareValue.sampleValue = 0;