I am using an FPGA to write into DDR memory attached to a tms320c6472 DSP using SRIO. This has largely been working, but I have run into a problem with chunks of data 128 bytes long not being written to.
The general flow is:
1. FPGA buffers 8272 bytes of data
2. FPGA issues SRIO writes into DDR address space in 256 byte chunks.
3. Once complete, DSP reads this data and performs processing
We initialized memory to a known value so we can see that roughly half of our transfers include 1 to 2 chunks of data that was not written. The location of these bad data chunks can vary, but the size does not.
I have inspected the SRIO status registers and there does not seem to be an error. Also, the FPGA sees ack responses to everything it sends. Are there any known issues with writing into DDR from SRIO? Is cache a potential issue? What DMA burst size does the SRIO peripheral use? We don't understand where the 128 byte data length is coming from.
Since the SRIO peripheral does all the work, I am at a dead end for debugging this issue.
Thanks
