My question is similar to this one: https://e2e.ti.com/support/arm/sitara_arm/f/791/t/361870
After reading SPRS612G (C6472 datasheet, reset section 7.7) and SPRU894J (C6472 DDR Memory Controller doc), it's not clear what state DDR will be left in for the various reset modes. Table 7-12 of the datasheet refers to memory content preserved (or not) but I would assume that refers to SRAM.
Is there a way to achieve a reset and keep DDR contents? Does it need to be a Warm reset so PLL3 keeps running? Any other considerations?
