RTOS: K2GEVM McASP0 Configuration Problem

Wujun He

Other Parts Discussed in Thread: PCM1864, 66AK2G02

Tool/software: TI-RTOS

Hi,

Thank you for your attention. We do project on K2GEVM board, based on the demo of K2G_bf_rt from the version SDK of processor_sdk_rtos_k2g_4_01_00_06.Our need is using McASP0 as Rx and McASP2 as Tx to get 8 mic signal through of 2 slices of PCM1864 codec and play one of 8 channels to the codec aic_3106 .

We are sure the configuration of codec PCM 1864 is correct because the data from PCM1864 is normal . The problem is configuration of McASP0, because there is no sound from Line Out( codec of AIC_3106)on the K2GEVM board .What we changed on McASP0 configuration of the demo K2G_bf_rt of hardware and software as the follow steps:

predef K2G_M001_A6x_Platform

1. McASP0 pinmux

/////////////////////// Cmb_STATUS cmb_AudioInit(void) ////////////////////////////////

#ifdef K2G_M001_A6x_Platform

/* MCASP1ACLKX, MCASP1AFSX, - PADCONFIG 155 to 156, added by HeWujun 2018.4.12 */

cmb_padMax = 156;

for (cmb_padCfg = 155; cmb_padCfg <= cmb_padMax; cmb_padCfg++)

{

cmb_pinMuxSetMode(cmb_padCfg, CMB_PADCONFIG_MUX_MODE_QUINARY);

// set to weak pull down

cmb_pullSetMode(cmb_padCfg, 0);

}

/* MCASP1AMUTE - PADCONFIG 158 */

cmb_pinMuxSetMode(158, CMB_PADCONFIG_MUX_MODE_QUINARY);

// set to weak pull down

cmb_pullSetMode(158, 0);

#endif

/* MCASP1AHCLKX - PADCONFIG 157 */

cmb_pinMuxSetMode(157, CMB_PADCONFIG_MUX_MODE_QUINARY);

// set to weak pull down

cmb_pullSetMode(157, 0);

////////////////////////////////////////////////////////////////////////////////

/* MCASP1AXR[0:3] - PADCONFIG 159 to 162 */

cmb_padMax = 162;

for (cmb_padCfg = 159; cmb_padCfg <= cmb_padMax; cmb_padCfg++)

{

cmb_pinMuxSetMode(cmb_padCfg, CMB_PADCONFIG_MUX_MODE_QUINARY);

// set to weak pull down

cmb_pullSetMode(cmb_padCfg, 0);

}

#ifdef K2G_M001_A6x_Platform

/* MCASP1AXR[4] - PADCONFIG 163, for DAC 3106 */

cmb_padMax = 163;

cmb_pinMuxSetMode(cmb_padCfg, CMB_PADCONFIG_MUX_MODE_QUINARY);

// set to weak pull down

cmb_pullSetMode(cmb_padCfg, 0);

#endif

//////////////////////////////////////////////////////////////////

2 .revise status = eDmaConfig() function and add handle to eDMA0;

////////////////// status = eDmaConfig() //////////////////////////

EDMA3_DRV_Result edmaResult = 0;

uint32_t temp;

// uint32_t temp0 ;

#ifdef K2G_M001_A6x_Platform

/* Enabling the dmaChannel MCASP1 Events to EDMACC1 (48 & 49) and

* Enabling the dmaChannel MCASP2 Events to EDMACC1 (50 & 51) */

temp=sampleEdma3GblCfgParams[1].dmaChannelHwEvtMap[1];

sampleEdma3GblCfgParams[1].dmaChannelHwEvtMap[1]= temp | 0x000F0000;

/* Enabling the dmaChannel MCASP0 Events to EDMACC0 (24 & 25) */

temp=sampleEdma3GblCfgParams[0].dmaChannelHwEvtMap[0];

sampleEdma3GblCfgParams[0].dmaChannelHwEvtMap[0]= temp | 0x03000000;

#else

/* Enabling the dmaChannel MCASP2 Events to EDMACC1 (50 & 51) */

temp=sampleEdma3GblCfgParams[1].dmaChannelHwEvtMap[1];

sampleEdma3GblCfgParams[1].dmaChannelHwEvtMap[1]= temp | 0x000C0000;

#endif

/* Initialize eDMA 0 */

hEdma0 = edma3init(CSL_EDMACC_0, &edmaResult);

if((hEdma0 == NULL) || (edmaResult != 0))

{

IFPRINT(cmb_write("eDMA instance 0 Initialization Failed\n"));

IFPRINT(UART_printf("eDMA instance 0 Initialization Failed\n"));

return (Cmb_EFAIL);

}

/* Initialize eDMA 1 */

hEdma1 = edma3init(CSL_EDMACC_1, &edmaResult);

if((hEdma1 == NULL) || (edmaResult != 0))

{

IFPRINT(cmb_write("eDMA instance 1 Initialization Failed\n"));

IFPRINT(UART_printf("eDMA instance 1 Initialization Failed\n"));

return (Cmb_EFAIL);

}

///////////////////////////////////////////////////////////////////////////////////////

/* Handle to eDMA */

extern EDMA3_DRV_Handle hEdma1;

/* added by HeWujun 2018.4.13 */

#ifdef K2G_M001_A6x_Platform

extern EDMA3_DRV_Handle hEdma0;

#endif

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

3. revise mcaspAudioConfig() function and some configuration information.

//////////////////////////////////////////////// status = mcaspAudioConfig(); ////////////////////////////////////////////////////////////////////////////////////////////////////////////

#ifdef K2G_M001_A6x_Platform

mcaspRxChanParam.edmaHandle = hEdma0; // added by HeWujun 2018.4.13

#else

/* Initialize eDMA handle */

mcaspRxChanParam.edmaHandle = hEdma1; // ori configuration for CMB

#endif

#if (CMB_AUDIO_DAC)

mcaspTxChanParam.edmaHandle = hEdma1;

/* Bind McASP2 for Tx */

status = mcaspBindDev(&hMcaspDevTx, CSL_MCASP_2, &mcaspTxParams);

if((status != MCASP_COMPLETED) || (hMcaspDevTx == NULL))

{

IFPRINT(cmb_write("mcaspBindDev for Tx Failed\n"));

IFPRINT(UART_printf("mcaspBindDev for Tx Failed\n"));

return (Cmb_EFAIL);

}

#endif // #endif K2G_M001_A6x_Platform

#ifdef K2G_M001_A6x_Platform

/* Added by HeWujun 2018.4.12, for K2G_M001_A6x_Platform */

/* Bind McASP0 for Rx */

status = mcaspBindDev(&hMcaspDevRx, CSL_MCASP_0, &mcaspRxParams);

if((status != MCASP_COMPLETED) || (hMcaspDevRx == NULL))

{

IFPRINT(cmb_write("mcaspBindDev for Rx Failed\n"));

IFPRINT(UART_printf("mcaspBindDev for Rx Failed\n"));

return (Cmb_EFAIL);

}

#else

/* Bind McASP1 for Rx */

status = mcaspBindDev(&hMcaspDevRx, CSL_MCASP_1, &mcaspRxParams);

if((status != MCASP_COMPLETED) || (hMcaspDevRx == NULL))

{

IFPRINT(cmb_write("mcaspBindDev for Rx Failed\n"));

IFPRINT(UART_printf("mcaspBindDev for Rx Failed\n"));

return (Cmb_EFAIL);

}

#endif

//////////////////////////////////////////////////////////////////////////////////////////////////////

McASP HW setup for receive and transmit information ,clock ,configuration as domo provide ：

///////////////////////////////////////////////////////////////////////////////////////////////////////

/* McASP HW setup for receive */

Mcasp_HwSetupData mcaspRcvSetup = {

/* .rmask = */ 0xFFFFFFFF, /* 16 bits are to be used */

/* .rfmt = */ 0x000180F0, /*

* 1 bit delay from framesync

* MSB first

* No extra bit padding

* Padding bit (ignore)

* slot Size is 32

* Reads from DMA port

* NO rotation

/* .afsrctl = */ 0X00000111, /* I2S mode - 2 slot TDM

* Frame sync is one word

* Externally generated frame sync

* Falling edge is start of frame

/* .rtdm = */ 0x00000003, /* slot 1 and 2 are active (I2S) */

/* .rintctl = */ 0x00000000, /* sync error and overrun error */

/* .rstat = */ 0x000001FF, /* reset any existing status bits */

/* .revtctl = */ 0x00000000, /* DMA request is enabled */

{

/* .aclkrctl = */ 0x00000080, /* Bit CLK Pol: falling edge, ACLKR is external */

/* .ahclkrctl = */ 0x00000000, /* AHCLKR is external */

/* .rclkchk = */ 0x00000000

}

};

/* McASP HW setup for transmit */

#if (CMB_AUDIO_DAC)

Mcasp_HwSetupData mcaspXmtSetup = {

/* .xmask = */ 0xFFFFFFFF, /* 16 bits are to be used */

/* .xfmt = */ 0x000180F0, /*

* 1 bit delay from framesync

* MSB first

* No extra bit padding

* Padding bit (ignore)

* slot Size is 32

* Reads from DMA port

* NO rotation

/* .afsxctl = */ 0x00000113, /* I2S mode - 2 slot TDM

* Frame sync is one word

* Falling edge is start of frame

* internally generated frame sync

/* .xtdm = */ 0x00000003, /* slot 1 and 2 are active (I2S) */

/* .xintctl = */ 0x00000000, /* sync error,overrun error,clK error */

/* .xstat = */ 0x000001FF, /* reset any existing status bits */

/* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */

{

/* .aclkxctl = */ 0X000000E3, /* Bit CLK Pol: falling edge, ASYNC is 1, ACLKX is internal, HF CLK to BCLK divider is 4 */

/* .ahclkxctl = */ 0x00000000, /* AHCLKX is external */

/* .xclkchk = */ 0x00000000

};

#endif

/* McAsp channel parameters for receive */

Mcasp_ChanParams mcaspRxChanParam =

{

0x0004, /* number of serializers */

{Mcasp_SerializerNum_0,

Mcasp_SerializerNum_1,

Mcasp_SerializerNum_2,

Mcasp_SerializerNum_3

}, /* serializer index */ /*Serial_4 ~Serial_7 is added by HeWujun 2018.3.31*/

&mcaspRcvSetup,

TRUE,

Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */

Mcasp_WordLength_32,

NULL,

GblErr,

2, /* number of TDM channels */

///Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,

Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_2,

TRUE,

TRUE

};

#if (CMB_AUDIO_DAC)

/* McAsp channel parameters for transmit */

Mcasp_ChanParams mcaspTxChanParam =

{

0x0001, /* number of serializers */

{Mcasp_SerializerNum_2,}, /* serializer index for DAC0 */

&mcaspXmtSetup,

TRUE,

Mcasp_OpMode_TDM,

Mcasp_WordLength_32, /* word width */

NULL,

GblErr,

2, /* number of TDM channels */

Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,

///Mcasp_BufferFormat_1SER_MULTISLOT_NON_INTERLEAVED,

TRUE,

TRUE

};

#endif

//////////////////////////////////////////////////////////////////////////////////////////////////////

4. On hardware .we change connection on K2GEVM and CMB . the original connection mode and changed connection mode as follow:

///////////////////////////////////////////////////////////////////////////////////////////////////////

the original:

changed connection mode:

The log dose not have error , software can be download on the 66AK2G02 and run without error; log as follows:

[C66xx]

******************************************

Audio Preprocessing Demo22

******************************************

This Demo Takes the Audio Input from 8 Mics from CMB

Runs the BF+ASNR+MSS+DRC Signal Processing Chain on Mic1 through Mic7

The Processed Audio Output will be Sent to Left Channels of K2G EVM On-Board Line-Out

The Mic8 will be Sent to Right Channels of K2G EVM On-Board Line-Out

Please Plug a Headphone to K2G EVM On-Board Line-Out

******************************************

cmb_cmb_pcm186xReset(), IIC 0 : addr = 0x94

K2G_M001_platform ReSet U2

cmb_cmb_pcm186xReset(), IIC 0 : addr = 0x96

K2G_M001_platform ReSet U3

K2G_M001_platform Set U2 in Master Mode

******************************************

Audio I2C0 0x96 U3 Configuration !

addr = 0x96 page = -1

in Writing Register = 0x0 data = 0x0

in Writing Register = 0x6 data = 0x41

in Writing Register = 0x7 data = 0x41

in Writing Register = 0x8 data = 0x44

in Writing Register = 0x9 data = 0x44

in Writing Register = 0xb data = 0x44

in Writing Register = 0x10 data = 0x0

in Writing Register = 0x11 data = 0x50

in Writing Register = 0x12 data = 0x0

in Writing Register = 0x13 data = 0x40

in Writing Register = 0x20 data = 0x1

cmb_pcm186xAdcInit() : In Page=0x0

cmb_AudioAdcInit_I2C0()...

cmb_AudioAdcSetGain_I2C0()...

..........................

cmb_AudioAdcConfigIntr_I2C0()...

DATA6 DATA7 Test !

******************************************

Audio I2C0 0x94 U2 Configuration !

addr = 0x94 page = 0

in Writing Register = 0x0 data = 0x0

in Writing Register = 0x6 data = 0x41

in Writing Register = 0x7 data = 0x41

in Writing Register = 0x8 data = 0x44

in Writing Register = 0x9 data = 0x44

in Writing Register = 0xb data = 0x44

in Writing Register = 0x10 data = 0x3

in Writing Register = 0x11 data = 0x50

in Writing Register = 0x12 data = 0x4

in Writing Register = 0x13 data = 0x40

cmb_pcm186xAdcInit() : In Page=0x0

cmb_AudioAdcInit_I2C0()...

cmb_AudioAdcSetGain_I2C0()...

..........................

cmb_AudioAdcConfigIntr_I2C0()...

DATA0 DATA1 Test !

mcaspAudioConfig : status = 0

But problem is no sound from LIND OUT on K2GEVM board . I do not konw why. I am not sure the McASP0 and McASP2 are correct and completely. The whole project is upload .Can you help me analyz and give me some suggestions for solving problems.The problem puzzled me for 2 days. I am long for your help . Thank you very much !

K2G_bf_rt_20180403.zip

Wujun He 2018.4.13

over 6 years ago

0 Cvetolin Shulev-XID over 6 years ago

TI__Guru 65405 points

The team is notified. They will post their feedback directly here.

BR
Tsvetolin Shulev

0 Ming Wei over 5 years ago

TI__Mastermind 41915 points

Hi Wujun,

I am confused by the following code segment in mcasp_cfg.c:

#if (CMB_AUDIO_DAC)
mcaspTxChanParam.edmaHandle = hEdma1;

#ifdef K2G_M001_A6x_Platform_
/* Added by HeWujun 2018.4.12, for K2G_M001_A6x_Platform */
    /* Bind McASP1 for Tx */
    status = mcaspBindDev(&hMcaspDevTx, CSL_MCASP_1, &mcaspTxParams);
    if((status != MCASP_COMPLETED) || (hMcaspDevTx == NULL))
    {
        IFPRINT(cmb_write("mcaspBindDev for Tx Failed\n"));
        IFPRINT(UART_printf("mcaspBindDev for Tx Failed\n"));
        return (Cmb_EFAIL);
    }
#else

...

Why you need to configure McASP1 for TX (to AIC3106)? Since you are using McASP0 (replacing McASP1) for RX (receiving from CMB) and McASP2 (same as the original demo) for TX. All you need to change is from McASP0 to McASP1 for RX. No changes are needed for TX. Because the AIC3106 is connected to the McASP2 on K2G EVM, if you change to McASP1 for TX, you will not get and audio output in Line Out.

Best regards,

Ming

0 Wujun He over 5 years ago in reply to Ming Wei

Intellectual 330 points

Hi Ming,

Thank you for browsing my post. hardware design of our first version product is use McASP0 as Rx and McASP1 as Tx . Before the demo has been run, the first version hardware design has been completed. Right now , we want do our project in two steps.

First step,we use K2G_bf demo on K2GEVM and CMB board ,using McASP0 as Rx ,McASP2 as Tx to make them work normally .

Second step,based on first step work ,we use McASP0 as Rx and McASP1 as Tx on our production ,in which McASP1 is connected AIC_3016.

We predef #ifdef K2G_M001_A6x_Platform in the project ,but #ifdef K2G_M001_A6x_Platform in the project_ is not defined ,so this part is not in use, it is for second step work ;

I have confused by the problem for a week , could you give me some suggestion on solving the problem. Thank you .

Wujun He. 2018.5.5

Processors

Processors forum

RTOS: K2GEVM McASP0 Configuration Problem