C6000 Multicore DSP

Browse by Tags

C6000 Multicore DSP

Welcome to the C6000 Multicore DSP Section of the TI E2E Support Community. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. To post a question, click on the forum tab then "New Post".

Sign In to Post
Tags
You have subscribed to this tag. To view or manage your tag subscriptions, click here.   Close
You have unsubscribed from this tag. To view or manage your tag subscriptions, click here.   Close
You are currently viewing:
6474 SRIO
Related Posts

  • Forum Post: DSPTMS320C6474 Cache Coherent function GSM ,Ftype used in SRIO

    tarik taro
    i wanna just to understand how can i implement cache coherent function GSM ( specially value indicated in Ftype of SRIO) thanks
    on Mar 16, 2010

  • Forum Post: C6474 SRIO to FPGA under DSP BIOS v6

    dkerns
    I've programed the DSP SRIO to be the host and the FPGA to send it's packets to the DSP via MAINT_WR. I have a "standalone" program that performs MAINT_RD/MAINT_WR/NREAD/NWRITE all successfully. When I take the identical program and make it a task (the only task running) under...
    on Apr 28, 2010

  • Forum Post: SRIO message passing C6474 problem

    jordan wolters
    Hello, We are 2 students and are currently evaluating Serial Rapid IO on an evaluation board (Spectrum Digital EVM) that features two TMS320C6474 DSPs. We are using the latest Code Composer version 4 to program the DSPs and read the registers. We are using Message Passing protocol to try sending a...
    on Dec 8, 2010

  • Forum Post: C6474 doorbell interrupt

    xiaoyan Bian
    Hi: I encounter some problem when testing the interface between the c6474 and c6455. Problem: C6455 sends a data packet to the c6474 and c6474 can receive the packet correctly,but when c6455 sends a doorbell interrpt packet to C6474,c6474 can not response the interrupt,that is c6474 can not enter...
    on Jun 7, 2011

  • Forum Post: Question about SRIO in C6474

    Kaiqi Yang
    If two different cores have the same transmit port,say lsu_conf.outPortId.Can they use SRIO to transfer data Simultaneously?Or there is something to do with the LSU block number?
    on Mar 26, 2012

  • Forum Post: Re: question of SRIO in C6474```

    Karthik Ramana Sankar
    Hi Kaiqi, Please, provide more details about your issue here. This will help us to provide better support. Are you using Direct IO or message passing? What platform are you running this test, Is it C6474 EVM? What type of SRIO errors you are encountering here?
    on Apr 12, 2012

  • Forum Post: Re: question of SRIO in C6474```

    Kaiqi Yang
    I am trying to trigger SRIO message passing on two different cores in the same DSP simultaneously,but the problem is some of those data can't be transfered.It's like there is a coflict between the transfer on two cores,I want to know how to solve this problem,Thank you!
    on Apr 14, 2012

  • Forum Post: Re: question of SRIO in C6474```

    Karthik Ramana Sankar
    Kaiqi, Is the SRIO message transfer from DSP1 (using only one core) to other DSP2 working successfully? Individually, you can verify DSP1 (core0) to DSP2 (core0) transfer and also DSP1 (core1) to DSP2 (core0) transfer. Do see any SRIO physical/logical layer related errors? Are all the descriptors...
    on Apr 16, 2012

  • Forum Post: question of SRIO in C6474```

    Kaiqi Yang
    In my project,I want to perform data transfer between two DSPs.But when I try to move data of core A and core B on DSP2 to core A on DSP1 simultaneously,the transfer of core A or core B in DSP2 cannot be triggered or sometimes the trasfer could be interrupted.Is there anyone who knows how to solve this...
    on Apr 11, 2012

  • Forum Post: Mapping SRIO congestion control packets to flows?

    Michael P
    I am trying to understand how a Serial RapidIO Congestion Control Packet (CCP) gets mapped to one of the sixteen flows in the ('C6474) SRIO peripheral. It seems fairly straightforward for flows 0 through 14: If the CCP comes from the destination identified in the register FLOW_CNTLn, it affects the...
    on Jun 21, 2012

  • Forum Post: RE: Mapping SRIO congestion control packets to flows?

    Karthik Ramana Sankar
    Hi Michael, Yes. Your understanding is correct. Therefore, "DestID of Flow 15, if all 0’s this table entry represents all flows other than flows 0 - 14". So setting it to 0 will count all incoming CCP Xoff/Xon for all DESTIDs not used in FLOW_CNTL_ID0-14. The above information will...
    on Jun 25, 2012

  • Forum Post: IACLIB without DSP/BIOS

    Kaiqi Yang
    Is there anybody has IACLIB for interDSP communication without DSP/BIOS?
    on Aug 6, 2012

  • Forum Post: RE: AIF on C6474

    Kaiqi Yang
    RandyP: By the way, in section 5.2 of "TMS320C6474 DSP Antenna Interface User's Guide", it refers line rates and data rates of SERDES, what the difference between them. And the data rates lists in the table is theoretical or practical?
    on Sep 2, 2012

  • Forum Post: RE: AIF on C6474

    Kaiqi Yang
    RandyP: No, I'm not using IACLIB, and I have downloaded the example with IACLIB, but it use OBSAI RP3(CPRI is required in my project). And I will appreciate it If you could offer me the IACLIB example in CPRI version. Now I am pretty sure that the timer couldn't be normally triggered in the...
    on Sep 3, 2012

  • Forum Post: RE: AIF on C6474

    Kaiqi Yang
    RandyP, Thanks for your help and the problem is solved perfectly. But I have another question to ask you. In my project, the FSync module of DSP1 and DSP2 are driven by same differential clock source on the board which is timer0 of DSP1. Here comes the question, if I want to implement inter-DSP communication...
    on Sep 6, 2012

  • Forum Post: C6474 SRIO DIO example code

    Jiajin An1
    Hi. I am using the EVM C6474 by Spectrum Digital. I have been trying to run the SRIO example project “srio_evm_dio_example” in the C6474 CSL I ran it according to the procedure described in readme.txt of this example. on Faraday #1 (SRC) I have seen the following output. It looks...
    on May 29, 2013

All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.

Content on this site may contain or be subject to specific guidelines or limitations on use. All postings and use of the content on this site are subject to the Terms of Use of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Terms of Use of this site. TI, its suppliers and providers of content reserve the right to make corrections, deletions, modifications, enhancements, improvements and other changes to the content and materials, its products, programs and services at any time or to move or discontinue any content, products, programs, or services without notice.

TI Worldwide | Contact Us | my.TI Login | Site Map | Corporate Citizenship | mobile m.ti.com (Mobile Version)

TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs and
embedded processors, along with software, tools and the industry’s largest sales/support staff.

© Copyright 1995-2013 Texas Instruments Incorporated. All rights reserved.
Trademarks | Privacy Policy | Terms of Use