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AIF
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  • Forum Post: Is FSYNC always required with AIF?

    ocv
    Hi, I will be using AIF for communicating with FPGA(through Fiber,point-point communication ) for bulk data transfer.Please let me know ,FrameSync is required in that case? Regards, OCV.
    on Sep 15, 2010

  • Forum Post: Re: C6474 SYS Clock vs FSYNC Clock

    Tom Johnson16214
    There is no requirement for maximum skew between these clock sources. The only requirement is for frequency coherency. Either one of the clocking solutions proposed will be acceptable. Skew matching is not needed between the SYSCLK and FSYNCCK signals.
    on Feb 18, 2011

  • Forum Post: Issues while Initializing AIF module on C6474 EVM

    Narendra Deshkulkarni
    Hello All, I am modifying an existing medical application running on C6474 EVM. I have to read data that are sent over 4 AIF lanes. For initializing the AIF, I am using an ABT library provided by TI. The ABT library aims at providing customer applications with an abstraction layer of TMS320C6474 AIF...
    on Feb 23, 2011

  • Forum Post: AIF problem

    Thanh Binh Tran
    when i try to run example code in : http://processors.wiki.ti.com/index.php/AIF_Inter_DSP_Communication with loop back : there is no problem but with non-loop back: i saw " PASS: Data matches perfectly. Size 0 bytes. Link0" . Although i didn't configure Link0. Only Link1, Link2...
    on Apr 9, 2011

  • Forum Post: How to implement AIF on EVM6474?

    XL Terrence
    hi, I am new to EVM6474. How can I implement AIF(CPRI or OBSAI) on the EVM6474 , so that DSP_1 on the board can send data to another DSP(DSP_2) or vice-versa. Is there any example to implement this inter-dsp communication? Thanks
    on Jul 13, 2011

  • Forum Post: C6474 Antenna Interface for Inter-DSP Communication

    Yu-Fu Hsieh
    Hi: We have designed our own C6474 target board which has 4 C6474 in it. I got IAClib version 1.5 and InterDSP_AIF_BIOS_Advanced_Example_1.5. Compiling, Linking, and Program loading are just fine. But, it only showed: 0 Main started 1 TX task: started 2 RX task: started Then it holds and...
    on Aug 22, 2011

  • Forum Post: Re: Probelms about AIF Inter DSP Communication

    Karthik Ramana Sankar
    Hi Chien, The Inter DSP AIF example provided in this thread above, should work with both C6474 and TCI6488 EVM. I got this example working successfully on TCI6488 EVM. Please, check your Endianess DIP switch settings on your EVM.
    on Apr 5, 2012

  • Forum Post: Re: Local oscillator in EVM6474.

    Karthik Ramana Sankar
    Hi Chien, The F1_SYSCLK(P/N) (61.44 MHz) and F1_SYNC_CLK(P/N) (30.72 MHz) are clocks related to AIF in C6474 EVM. The F1_SYSCLK drives the AIF SERDES and the F1_SYNC_CLK provides the required synchronization signals. For more details refer to Figure 2-2 of C6474 EVM technical reference manual: ...
    on Apr 9, 2012

  • Forum Post: Re: Probelms about AIF Inter DSP Communication

    Karthik Ramana Sankar
    dien bk36, The data output of the AIF module is I/Q symbols. These I/Q symbols will be provided to the radio module for transmission. My understanding is that, the radio module will be using a carrier frequency for transmitting on the air. What do you mean by " frequency carrier of AIF module"...
    on Apr 9, 2012

  • Forum Post: RE: CPRI Interface between 6474 DSP and Xilinx FPGA

    Ahmet Caliskan
    Hi Albert I have been working for four days on synchronizing DSP and FPGA, but I couldnt handle the problem. I see, L1 synchronization is established and Protocol version setup is done between DSP and FPGA but than FPGA enter the Passive Mode and the link stay in Passive Mode. I see Tx MAC is in...
    on Jul 28, 2012

  • Forum Post: CPRI Interface between 6474 DSP and Xilinx FPGA

    Ahmet Caliskan
    Hi e2e.ti users, I have a strong problem with CPRI interface berween 6474 DSP and FPGA.. Spartan 6 FPGA withCPRI IP Core V4.1 is used. 1X Link (614.4 Mbps) is used. FPGA is the CPRI Master (REC) and DSP is the Slave (RE). I tested CSL_6474 AIF example codes on DSP. "aif_cpri_lbk_generic_4x_15bit_short_frame"...
    on Jul 23, 2012

  • Forum Post: How to determine the data reception is completed in AIF communication?

    Kaiqi Yang
    Hi, guys! I'm using AIF to perform data transfer between two DSP on TMS320C6474 , and the program works well. But the program is based on the assumption that the receiver already knows the amount of data,and when it receives enough data, the program reaches a software breakpoint. My question is,...
    on Oct 8, 2012

  • Forum Post: Antenna interface clock generation circuit of the EVM6474

    Dieter Spaar
    Hello, I am interested in using the EVM6474 for OBSAI/CPRI evaluation. Is there a specific reason why the clock generation circuit for the Antenna Interface isn't populated, e.g. wouldn't the circuit work as drawn in the schematics ? I ask because I am thinking about populating the missing parts...
    on Nov 23, 2012

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