C6000 Multicore DSP

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C6000 Multicore DSP

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C66x
Related Posts

  • Forum Post: Re: IDMA bandwidth

    Yishay Hayardeni
    Chad, I'm using Release code with -o3 optimization. The TimeVal[] data block is located in the L1D. My Cache setting are: L2 Cache -128K, L1D Cache - 16K, L1P Cache - 16K L1DBuff is in the L1D, L2Buff is in the L2. I also ran the whole routine in the L1P so there will be no cache issues...
    on Aug 18, 2011

  • Forum Post: Re: Mixed Radix FFT

    Xie qunfang
    http://www.ti.com/litv/pdf/sprugs2a can't be found. I'm looking for libraries for LIE FFTs...Does C66X DSPlib contains any ? Thanks
    on Oct 6, 2011

  • Forum Post: Re: Mixed Radix FFT

    Xie qunfang
    Could you give me some suggestions about how to LTE FFTs using FFTC? I'd like to programming at CCSv5 platform. But I didn't find any info. on how to program.
    on Oct 8, 2011

  • Forum Post: Re: Mixed Radix FFT

    Xie qunfang
    Thank you very much ! I'm downloading MCDSK now! Is there any FFT benchmark for C66X DSP ? I saw FFTC benchmark in C6670 at E2E community, but how about C6678 etc , there is no FFTC in them , I want to know the performance of them while computing FFT.
    on Oct 13, 2011

  • Forum Post: Re: Mixed Radix FFT

    Xie qunfang
    Thanks and I 've got the test results of each instruction of C66X , but there is only computing cycles when N=128 and 256 , what about N=512,1024 or even more points ?
    on Oct 14, 2011

  • Forum Post: Setting up l2 cache, ndk stack problems

    Andy Faithfull
    I am having trouble with a udp socket. It receives for a random time, then stops working and can even cause a crash. I read in the ndk faqs that the ndk drivers need some l2 cache, and my configuration does not have any allocated. When I try to set the cache size to anything other than 0, I get this...
    on Sep 2, 2011

  • Forum Post: Re: Clear SRIO LSU transactions using PRVID.

    Chaitanaya Chhibbar
    Thanks Travis for the information.. I have tried to release the using the privid 0 for core 0 but that is not working... - LSU 0 is being used by core 0 Is there any thing else which i need to do with this or does it require some time to release the shadow registers ? eg. privID...
    on Jan 20, 2012

  • Forum Post: Re: Clear SRIO LSU transactions using PRVID.

    Chaitanaya Chhibbar
    Hi Travis, Thanks for the reply... I have tried the below procedure but its not working. Kindly help me to figure out the issue. ---> One Lsu is dedicated per core i.e. only if Lsu 0 is being used by core 0 then no other core uses it. Operation details: 1. Make sure there is space...
    on Jan 28, 2012

  • Forum Post: NWRITE and NWRITE_R transactions taking more time then NREAD ( Throughput Measurement - DIRECTIO )

    Chaitanaya Chhibbar
    Hi, I have measured the throughput for different SRIO - direct IO transaction formats for TI DSP - 6618 using the bridge board setup. Problem Statement: Nread gives better throughput then Nwite and NwriteR. Measurement Setup: DSP on EVM 1 connected to DSP on EVM 2 using bridge board. ...
    on Mar 23, 2012

  • Forum Post: IDMA bandwidth

    Yishay Hayardeni
    Hi, I'm using a C6678 device. I tested the IDMA transfer rate for L2 to L1D transfers (using IDMA1). From my understanding the internal bus of the L2 and L1D memories is 256bit wide and it works on the EMC clock which is half of the DSP clock. This gives a theoretical bandwidth of 16GB/sec (for...
    on Aug 4, 2011

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