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EDMA3
Related Posts

  • Forum Post: C6474 porting Mcpsp_Edma_example to DSP/BIOS

    gareth james
    I am trying to use the Mcbsp_Edma_example sample code from the EVMC6474_V1\csl_C6474\examples\mcbsp\mcbsp_edma directory, but need to port it to a DSP/BIOS environment. The code as it stands works. I am having difficulties porting it to a DSP/BIOS wrapper. The area that I think I am having problems...
    on Jun 17, 2009

  • Forum Post: Re: TCI6486: EDMA3 signals transfer is complete but no data is actually written

    Gilad Barzilay
    Never mind, found it - seems that since the EDMA is outside the megamodules you can't use local addressing, but need to convert to global addresses instead, or you get undefined behaviur.
    on Oct 6, 2010

  • Forum Post: How to use EDMA for SRIO transfer on c6455/6474

    SNBANIK
    I have been running SRIO CSL examples on c6455 EVM - transferring data from one DSP to the other. The example uses programmed transfer using NWRITE (that is the DSP CPU writes to the SRIO LSU register 5 to cause the transfer). My need is to transfer big chunks (say a frame size of 256KBytes) continously...
    on Sep 15, 2009

  • Forum Post: Re: Dose this inter-core communication exist?

    Kaiqi Yang
    Could you give me an example of inter-core communication using DMA transfer on C6474 or C6472? Regards, Uni
    on Mar 7, 2011

  • Forum Post: Re: Puzzled by EDMA3

    Kaiqi Yang
    I mean is the total data rate of EDMA3 equals to all 6 TCs put together?
    on Apr 2, 2011

  • Forum Post: Puzzled by EDMA3

    Kaiqi Yang
    EDMA3 has 6 queues and 6 EDMA3TCs,does this mean there could be up to 6 transfers at the same time cause for every Q/TC there could only be one transfer at the same time?
    on Apr 1, 2011

  • Forum Post: About EDMA3 on C6474

    Kaiqi Yang
    From sprug11,we konw that the maximum value of ACNT is 65535 and valid values for SRCBIDX are between –32768 and 32767.But when I set ACNT to 65535 and set BCNT to 4,what the value of SRCBIDX should be?
    on Apr 18, 2011

  • Forum Post: Efficient use of C6455+ SRIO with EDMA

    Joseph Gagnon
    I am attempting to establish an SRIO data communication infrastructure that will split a large data block into multiple LSU-sized parcels and make the most efficient use of the SRIO bandwidth possible with minimal DSP resources consumed. I will be using all 4 LSUs with NWRITE_R to ensure data integrity...
    on May 9, 2011

  • Forum Post: C6472 TSIP data sorting

    soldsp
    Hi, I'm in the planning phase of driver design for the C6472 TSIP. By reading the TSIP user guide, I find out the TSIP's DMA don't allow data sorting. The DMA copy data frame per frame. For my application, I need the data sorted per TimeSlot in order to have related data in contiguous...
    on May 12, 2011

  • Forum Post: SL2RAM uDMA3

    khaled saab
    Hi, I'm using a C6472 DSP chip. in order to move data between the different cores, we are using a section of the SL2RAM as shared memory. The source core put data into that section and the destination core reads it back. the IPC registers (IPCGR and IPCAR) are used to send semaphores between...
    on Apr 26, 2011

  • Forum Post: Re: SL2RAM uDMA3

    khaled saab
    Thanks Estian. The DAT_copy( ) is exactly what I need. However, I tried to run the DAT example on a C6472 with no success . The example that I tried came with the CSL library csl_c6472/example/dat/src/Dat_example.c (see http://focus.ti.com/docs/toolsw/folders/print/sprca03.html ) . There is...
    on May 27, 2011

  • Forum Post: Enforcing pointer alignment

    Manu Bansal
    Hi, I'm programming the VCP2 on a C6474 multi-core platform and my hunch is that I am running into input or output buffer misalignment problems. My code runs with some buffer length (and advance stride) settings, but fails with others. EDMA3 transfers need to be double(?) word-aligned. In general...
    on Jul 12, 2011

  • Forum Post: Using EDMA3 with BIOS 5.41 (Using Code Composer Studio Version 4.2.3 and C6748 processor)

    Debarati Kundu
    Hi, I am planing to develop some codes using EDMA3 (with/without BIOS 5.41), Code Composer Studio Version 4.2.3 and C6748 (OMAPL138)processor. I want to develop a sine wave generation by storing the sine values for one cycle in a table and then repeatedly transferring the entries of the table by self...
    on Jul 27, 2011

  • Forum Post: EDMA3 can't be triggered

    Kaiqi Yang
    A part of my program： #include #include #include #include #include #include #include #include #include #include #include "3rnds.c" #define BUF_SIZE_W 6 #define NUM_CORES 2 #pragma DATA_SECTION(breceive,".breceive_section"); #pragma...
    on Oct 12, 2011

  • Forum Post: Some problem about EDMA3

    Kaiqi Yang
    I want to transfer 65536 btyes of data in two bcnts,and each bcnt contains 32768 bytes,but the result is I can only receive the first bcnt,is there any problem?Below is part of my program: myParamSetup.srcAddr = (Uint32)pm; myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(32768,2); myParamSetup.dstAddr...
    on Nov 17, 2011

  • Forum Post: Configuring reload on TPCC - EDMA

    Paulo Villani
    I'm using EMDA with manual trigger to write on McSPI port. But even setting BCNTRLD, BCNT is not reloading. How I configure auto-reload on a logical channel ? Below is the code as I am currently setting up the EMDA: // Destination Start Address (McSPI2_TX_CHO) *( &TPCC_BASE + TPCC_DST...
    on Dec 19, 2011

  • Forum Post: C6472 (porting MIDAS OCT from C6678) EDMA3_RM_open returns 0xffffff62

    Stefanos A.
    Hello, I am trying to port the MIDAS OCT demo from the C6678 to the C6472 and I am now stuck at an issue that I cannot seem to fix: a call to RMAN_assignResources fails with status=7 (IRES_ENORESOURCE). The trace log indicates that the issue stems from a call to EDMA3_RM_open which fails with error...
    on Jan 10, 2013

  • Forum Post: L1D and LL2 cache coherency when using EDMA3

    SNBANIK
    Processor Used: c6472. We have a situation where we suspect we could be hitting a L1D to L2 cache coherency issue but not sure. We use all of L1D as cache. We have a (temporary) processing buffer (significant size) in LL2. The final output buffer is in DDR2. We use EDMA3 to transfer the processed...
    on Apr 2, 2013

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