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SRIO
Related Posts

  • Forum Post: C6474 sRIO Error Info Questions

    TommySong
    There is a sRIO failure case that has below error info: Logical/Transport Layer Error Detect CSR register (offset 2008) value: 0x01800000. That indicates there are PKT_RSPNS_TIMEOUT and UNSOLICITED_RSPNS. Port 0 Error Detect CSR register (offset 2040) value: 0x80500005. That indicates there...
    on May 19, 2010

  • Forum Post: Compilation error from DIO_lib.

    ocv
    Hi, I am using DIO libraries for doing the SRIO enumeration in C6474 EVM.I used the same .tcf file mentioned in testDIO_tcpFarm project.But it gives the following error while compiling. [testDIO_tcpFarm.tcf] "C:\CCStudio_v3...
    on Jul 12, 2010

  • Forum Post: C6472 DEVSTAT_KEY

    Peter Robertson
    I am trying to use SRIO on a C6472 system. After much wasted time, I have been informed by TI support that the device needs to be enabled by writing to DEVSTAT and DEVSTAT_KEY. I have searched the TI documentation and this site but have been unable to find any reference to DEVSTAT_KEY. DEVSTAT...
    on Nov 8, 2010

  • Forum Post: How to use EDMA for SRIO transfer on c6455/6474

    SNBANIK
    I have been running SRIO CSL examples on c6455 EVM - transferring data from one DSP to the other. The example uses programmed transfer using NWRITE (that is the DSP CPU writes to the SRIO LSU register 5 to cause the transfer). My need is to transfer big chunks (say a frame size of 256KBytes) continously...
    on Sep 15, 2009

  • Forum Post: Re: TMS320C6474 SRIO Error

    tscheck
    I'm guessing if you only shut one DSP down, you are either running into the case where Port_OK never gets set, or the ACKIDs aren't aligned after you restart. Read Appendix B of: http://focus.ti.com/lit/ug/sprug23d/sprug23d.pdf for a better description. If you are using the latest MCSDK CSL from...
    on Mar 25, 2011

  • Forum Post: Re: C6474 SRIO Message Transfer(Receive)

    tscheck
    Tony Q1: If the all fields of RXU_MAP_Ln and RXU_MAP_Hn registers have same settings except QUEU_ID, which register has high priority ? RXU_MAP_L0/RXU_MAP_H0 are checked at first and QUEU_ID of first matched register is used, for example. Yes, you are correct. The first matching register set is used...
    on Apr 8, 2011

  • Forum Post: Efficient use of C6455+ SRIO with EDMA

    Joseph Gagnon
    I am attempting to establish an SRIO data communication infrastructure that will split a large data block into multiple LSU-sized parcels and make the most efficient use of the SRIO bandwidth possible with minimal DSP resources consumed. I will be using all 4 LSUs with NWRITE_R to ensure data integrity...
    on May 9, 2011

  • Forum Post: Re: SRIO SPn_ERR_STAT error bits

    tscheck
    Hello, If the port never becomes initialized, there is something fundamentally wrong in the configuration or hookup. I'm assuming that you have the DSP able to communicate with another DSP, or in loopback. If that is true, then things I would check are: make sure the data rates are equal on both...
    on May 13, 2011

  • Forum Post: SRIO SPn_ERR_STAT error bits

    SNBANIK
    We are trying to get SRIO connection going between c6472 EVM and Stratix4 EVM. We are getting error bits set in the DSP SRIO register SP0_ERR_STAT (we are using port 0 for now). The bit that is always set (to 1) is bit0 which is PORT_UNINITIALIZED. There are other bits that are sometimes set...
    on May 12, 2011

  • Forum Post: Re: evm6474 bootloader procedure

    tscheck
    A SRIO boot example can be found at: http://processors.wiki.ti.com/index.php/C6474 click on the Boot Test Package link. Regards, Travis
    on May 17, 2011

  • Forum Post: SRIO back pressure question on c6472

    SNBANIK
    I have a situation where the DSP (c6472) sends 2D frames out to the Back End (BE) DDR memory. I have setup the SRIO for peak data transfer rate of 2.5 Gbps (3.125 Gbps with 10/8). That leads to a data transfer BW of 300MBytes per second plus. The DDR in the BE could sometimes be in a state where it can...
    on Jun 30, 2011

  • Forum Post: TMS320C6474 SRIO with SRIO Switch(TSI578)

    pubesh r
    Hi All, we are developing custom board using TMS320C6474 DSP,SRIO implementation with IDT TSI578 SRIO Switch. We have used 6 TMS320C6474 dsp's on board and they are connected to one SRIO switch. Assuming Dev id of DSP 1 as 0x01,DSp 2 as 0x02....dsp 6 as 0x06 and based on our schematic connections...
    on Oct 14, 2011

  • Forum Post: Question about Inter-communication on c6474

    Thuong Nguyen Canh
    Hi all, My project is implement functions in one core and then send the real time data to another core between an DSP. I try to use SRIO to communicate between two core, but I can't find the evm6471v1 folder. I'm using CCS 3.3 Thanks a lot.
    on Nov 22, 2011

  • Forum Post: SRIO manual and circular buffering

    Dirk Buijsman
    On page 65 of the C6474 SRIO manual (sprug23) it states: " There are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers. ". What is meant with "circular buffers" here? The manual further mentions " TID circular buffers "...
    on Nov 7, 2011

  • Forum Post: Re: SRIO manual and circular buffering

    Dirk Buijsman
    Thanks for confirming Travis, I just to make sure I was using it the right way. Especially datasheets as big as the SRIO one sometimes contain "mysterious" references. This forum is great for clearing up things the datasheets are not explicit about. Cheers, Dirk
    on Jan 13, 2012

  • Forum Post: Re: Clear SRIO LSU transactions using PRVID.

    Chaitanaya Chhibbar
    Thanks Travis for the information.. I have tried to release the using the privid 0 for core 0 but that is not working... - LSU 0 is being used by core 0 Is there any thing else which i need to do with this or does it require some time to release the shadow registers ? eg. privID...
    on Jan 20, 2012

  • Forum Post: Re: Clear SRIO LSU transactions using PRVID.

    Chaitanaya Chhibbar
    Hi Travis, Thanks for the reply... I have tried the below procedure but its not working. Kindly help me to figure out the issue. ---> One Lsu is dedicated per core i.e. only if Lsu 0 is being used by core 0 then no other core uses it. Operation details: 1. Make sure there is space...
    on Jan 28, 2012

  • Forum Post: SRIO configuration on c6474

    Akhilesh Khemka
    Hi, I have a design issue while configuring SRIO on TI 6474 multicore DSP. I have to use SRIO in the Direct IO mode. As per the requirement, 2 cores of the DSP would be sending data in Downlink to a common FPGA over SRIO interface. I plan to bind these 2 cores to 2 of available 4 LSUs (i.e, core...
    on Mar 5, 2012

  • Forum Post: Re: question of SRIO in C6474```

    Karthik Ramana Sankar
    Kaiqi, Is the SRIO message transfer from DSP1 (using only one core) to other DSP2 working successfully? Individually, you can verify DSP1 (core0) to DSP2 (core0) transfer and also DSP1 (core1) to DSP2 (core0) transfer. Do see any SRIO physical/logical layer related errors? Are all the descriptors...
    on Apr 16, 2012

  • Forum Post: RapidIO - C6472: what are the SRIO read time specs?

    Eddie3909
    Hi C6472 Our system is timing out on single word reads from the DSP SRIO port. We have an FPGA reading a DSP DDR2 word and sometimes the read time is over 500 usec before we get a response. Granted the DDR2 bus is busy because the DSP CPUs are crunching DDR2 data, but doesn't 500 usec for a single...
    on Aug 7, 2012

  • Forum Post: SRIO debug problem on C6474

    JP
    Hi , I'm using SRIO between a C6474 processor and an IDT switch. It works quite well. However I notice a behaviour that I can't explain when I use the CCS5 debugger through a XDS560v2 STM Jtag Pod. The experiment described next has been configured to verify the flow control mechanism. 1...
    on Sep 19, 2012

  • Forum Post: SRIO SWITCH

    Avinash Neethi1
    Hi, We were trying to configure the SRIO Switch for 2.5Gbaud. But we can able to configure only for 1.25Gbaud. We can't able to perform the internal-loopback in C6678 through SRIO switch in c6678(REV-2.0) . But we can able to perform the internal-loopback in C6678 through SRIO switch in c6678...
    on Feb 27, 2013

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