TI E2E Community
Digital Signal Processors (DSP)
C6000 Multicore DSP
Keystone Multicore Forum (C66, 66A, AM5)
As far as I understand, the smartrelex allow the system to lower the CVDD voltage in order to reduce power, according to the DSP performance.
1. Can I use a fixed 1.1V power supply instead of the smartflex adjustable power supply? (I think it's like class-0 mention in sprabi2) ?
2. If not using the smart flex, can I leave the relevant pins (VCL, VD, VCNTL0-3) floating?
3. If I drive CVDD from the same power supply of CVDD1 (e.g. 1V fixed), what is the degradation in the DSP performances I will get?
4. We are using DSP bios, does smartflex supported in the DSP bios?
You must use SmartReflex and a fixed power supply solutions is not permitted.
SmartReflex is not an OS implementation, it is a HW implementation.
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Does that mean C6678 can control the smart reflex automatically?
If I should control smartreflex by code,why can't I use a fix power supply for CVDD instead?
It's controlled by HW, which means the C6678 will control what voltage level that particular device needs for proper operation and also staying within the power spec. There is NO SW control of the (i.e. the CorePac inside the DSP cannot program what this value will be, it's burned into e-fuse during production test.) We only support the device with smart reflex. You can not use a fixed power supply for CVDD.
DSP register 014 contains this burned-on-chip value for CVDD and it is accessible from the program. I am thinking to use this feature by eliminating the hardwired VCNTL0-3 and using I2C to control another Power Supply Manager - LTC2978. It has though more user friendly programming tool LTPowerPlay and 8ch.(ADCs & DACs) The only thing I have to give up is the Class-3 operation of the SmartReflex, so the voltage won't be dynamically controlled.
Tell me if I am missing sommething
I'm not sure where you got this information, but the VID value isn't available via DSP register. Even if it where, you'd need to boot the device and execute code w/ whatever the initial CVDD value was. If it's to low, you can have a failure and it won't boot at all (the SmartReflex logic circuit will operate at the initial voltage even if the cores won't properly operate) and if the initial voltage level is set too high, you can exceed the power limitation of the board and have a power brown out before you complete this operation and set the voltage to the VID values.
Can we make Class 3 operation of the SmartReflex for 6678 (4b VID) by continuously check VCNTL[0:3] (ex, by FPGA polling) and periodically set CVDD voltage point via PMBus (aka SmartReflex Class 3 via I2C)
Polling the VCNTL[3:0] signals can be done to implement a Smart Reflex power supply solution. You could poll this by control logic such as in an FPGA or by a small microprocessor such as an MSP430. Since it is a 2-phase interface, you would need to sample the VCNTL[3:0] pins at least once every 30us to guarantee that you do not miss a voltage command. Use of an FPGA or an MSP430 to sample the VID values and then to translate this into a PMBUS protocol is a very complicated solution. A digital power solution using either the UCD9222 or UCD9244 controllers provide a feature rich solution that supports active monitoring as well as loop control characteristic adjustments through a configuration file change. If a basic DC-DC supply implementation is desired, you can use the LM10010 to capture the VID values and it drives a DAC output that can connect to any analog power controller such as the TPS56121. Example schematics for these digital and analog power solutions are available.
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Thanks for help!
Can we start at fixed CVDD voltage point and then debug own VCNTL2PMBus Loop at initial phase of project. Which starting value applicable? Can we use value according to VCNTLID register in Boris posts as Class 0 operation?
We are currently recommending that the initial voltage be 1.0V. This will be sufficient until the VCNTL control output can be latched.
Regarding the VID value available at 0x14 in the PSC memory map. This value is provided for debug purposes only. It is defined in the PSC UG in Figure 3-2 where bits 21:16 are the only valid bits containing the 6-bit VID value. This register is not intended to be used for any type of software-based Smart Reflex control. The VCNTL pin output must be latched and used to control the voltage long before software is executing on the core or an external master such as I2C can access this internal register.
1. "We are currently recommending that the initial voltage be 1.0V" - Could you please tell in which document this is mentioned?
2. "This will be sufficient until the VCNTL control output can be latched" - What is the maximum time allowed (to hold Vcore fixed at 1.0V) until VCNTL control output can be latched?
Unfortunately, the information in this e2e thread is stale. Soon after the posts in April 2012 we discovered through device characterization that the initial voltage needs to be the maximum allowable Smart Reflex value of 1.1V. This value will be sufficient until the VCNTL output which will set the optimum operating voltage for that individual device. This is true for all KeyStone-I devices. This information will be contained in the next version of the Hardware Design Guide that is currently being revised. Please see the attached notification.
7840.Programmation of CVDD rail power supplies.pdf
Thank you Tom!
1. Does this notification appear on TI.com? If yes, please send us a link...we are interested to check all notifications related to the C6678 DSP.
2. So, for C6678 DSP we will use initial voltage of 1.097V (VCNTL #62).
3. What is the maximal time limit to hold the SmartReflex Vcore at 1.1V? We have time delay until the VCNTL output is ready. This delay is due to power-up sequence and a voltage translating buffer (1.8V to 3.3V) with HiZ control for the VCNTL signals. We want to be sure that our timing is within constraints.
#1. It appears that this is not on TI.com yet. we are working to get this corrected.
#2. You can use VID code 63 which produces 1.103V. This is within tolerance of 1.10 +/-5%.
#3. The VId code appears on the VCNTL output pins soon after reset is released. This time period is not characterized but it is much less than a second - on the order of 10 to 100ms. The power supply must latch and transition to the new voltage immediately (within a few milliseconds) after it is presented. Acceptable delays in power sand reset equencing will not violate these time constraints. Note that the device must not be held in reset for long periods of time as indicated in subsection "220.127.116.11 Prolonged Resets" in the C6678 Data Manual.
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