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Ya,

Hopefully, the below information will be adequate until the performance application note is published.

All throughput figures listed below assume that the DSP is operating at 1 GHz (1000 Mhz).

Raw Memory Throughput:

• L1D SRAM: L1D operates at DSP/1 frequency, so it can be accessed every cycle. L1D is accessed through a 256 bit interface, so the maximum throughput of L1D is 32,000 megabytes per second. ((256 bit buswidth)/(8 bits/byte)*(1000M)=32000MB/s)
• L2 SRAM: L2 operates at DSP/2 frequency, so it can be accessed every other cycle. L2 is accessed through a 256 bit interface, so the maximum throughput of L2 is 16,000 megabytes per second. ((256 bit buswidth)/(8 bits/byte)*(1000M/2)=16000MB/s)
• MSMC SRAM: MSMC operates at DSP/2 frequency, so it can be accessed every other cycle. MSMC has 4 memory banks, each of which is accessed through a 256 bit interface. All 4 banks can be accessed simultaneously by separate cores or other system masters. If the data in MSMC SRAM is allocated so that each of the 4 banks are being fulling utilized simultaneously, the maximum throughput of the shared memory is 64,000 megabytes per second. ((256 bit buswidth)/(8 bits/byte)*(1000M/2)*(4 banks)=64000MB/s). Up to 4 masters can access MSMC simultaneously.
• DDR3: DDR3 data is accessed through a 64-bit interface. Assuming that DDR3-1333 is operating at the maximum rate, the theoretical maximum throughput 10,664 megabytes per second. ((64bits)/(8bit/byte)*(1333M)=10664MB/s). Only one master can access the DDR3 at a time.

Maximum Throughputs for C66x core and DMA masters:

• C66x Core: (128 bit buswidth)/(8bit/byte)*(1000M)=16000MB/s
• IDMA: (256 bit buswidth)/(8bit/byte)*(1000M/2)=16000MB/s
• EDMA0: (256 bit buswidth)/(8bit/byte)*(1000M/2)=16000MB/s
• EDMA1: (128 bit buswidth)/(8bit/byte)*(1000M/3)=5333MB/s
• EDMA2: (128 bit buswidth)/(8bit/byte)*(1000M/3)=5333MB/s

DDR3 Accesses using EDMA:

If you use EDMA0 to access DDR3, then you should be able to get data at a maximum rate of 10664 megabytes per second, excluding any idle time required for setting up the EDMA transaction. If using EDMA1 or EDMA2 to access DDR3, then the maximim rate that you can get data from DDR3 is 5333 megabytes per second, exculding any idle time required for setting up the EDMA trasaction.

C66x Core Accessed to DDR3:

Assuming that L1D, L2, and MSMC are all configured as SRAM (caching disabled) then single reads to DDR3 will stall the DSP 89 cycles. Burst reads to DDR3 will stall the DSP 43.2 cycles. Writes to DDR3 will not stall the DSP since the data will be written to DDR3 by the DDR3 controller; however, it will take some time for the data to actually arrive in DDR3.

Regards,

Derek