TI E2E Community
Digital Signal Processors (DSP)
C6000 Multicore DSP
Keystone Multicore Forum (C66, 66A, AM5)
Why the data in MSMC can't be cached in L2 cache?
I set the cache size: L1P 16K, L1D 32k, L2 256K.
I place a buffer in MSMC SRAM, I read the buffer data,do some calculate, then store the result to another buffer in DDR3.
I view the address 0x0c000000 at the "memory Browser" window of CCS5, After read the buffer data, the data is cached by L1D cache(show in the first picture), but after the data is eviction from L1D cache, the memory Browser window show the buffer data isn't in L2 cache(show in the second picture), Why?
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It should not be necessary to cache the MSMC in L2 because the MSMC RAM is hooked up "close" to the CorePAC. Why do you think it is necessary to cache the MSMC?
It is technically possible to cache the MSMC SRAM in the L2 cache by remapping the MSMC RAM using the XMC MPAX (Memory Protection and Address Extension) unit. For example, you could use the XMC MPAX to remap 0xF0000000 to 0x0c000000, then you can control the cachability of 0xf0000000 via MAR240. This process is normally done to make a non-cachable (in L1D) area of MSMC, not to make MSMC cacheable in L2, but it works both. This remapping operation increases the distance to the MSMC and will slow down accesses which miss the cache via the remapped address, compared to accesses made directly through the 0x0c000000 path.
If you choose to try this, it is legal to access the MSMC from either path. However, it is strongly recommended to access each 128 byte block of MSMC from only one path, since the L2 cache is not coherent between the two paths.
The MPAX and MAR registers are documented in the CorePac user guide (http://www.ti.com/lit/sprugw0). The MAR registers are in chapter 4, and the MPAX is in chapter 7.
The relevant functions for these registers are in <ti/csl/csl_xmcAux.h> and <ti/csl/csl_cacheAux.h>
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