I have 2 6678L card( version V1.0 and V0.3 ). I want to communicate each other through PCIe on AMC connector pins below.6678L Card v1.0 6678L Card v0.3 ----------------- ----------------- 80 PCIE_REF_CLK_P => 80 PCIE_REF_CLK_P 81 PCIE_REF_CLK_N => 81 PCIE_REF_CLK_N 44 AMCC_P4_PCIe_TX1P => 47 AMCC_P4_PCIe_RX1P 45 AMCC_P4_PCIe_TX1N => 48 AMCC_P4_PCIe_RX1N <= 47 AMCC_P4_PCIe_RX1P <= 44 AMCC_P4_PCIe_TX1P 48 AMCC_P4_PCIe_RX1N 45 AMCC_P4_PCIe_TX1N 50 AMCC_P5_PCIe_TX2P => 53 AMCC_P5_PCIe_RX2P 51 AMCC_P5_PCIe_TX2N => 54 AMCC_P5_PCIe_RX2N 53 AMCC_P5_PCIe_RX2P <= 50 AMCC_P5_PCIe_TX2P 54 AMCC_P5_PCIe_RX2N <= 51 AMCC_P5_PCIe_TX2N "PCIE_exampleProject" in MCSDK188.8.131.52 - PDK 184.108.40.206 is loaded two 6678 card.Q1-) Is this connection is true, I don't want to damage 6678 PCIe driver.Q2-) In this configuration CLK will be generated by only one card (v1.0), V0.3 card is slave. Therfore, I disabled "pcieSerdesCfg" function for program in V0.3 card. There is no change for program in 6678 V1 cardIs this configuration true?Best RegardsGoksel
You can connect a pair of C6678L EVMs for comunication over the PCIe interfaces. One will be configured as the root complex and one will be configured as an endpoint.
The EVM does not support the option to drive a PCIe reference clock on pins 80/81. These pins only support clock into the EVM. However, for the configuration you are trying to operate, both EVMs can operate on their local internal PCIe reference clocks.
How are you connecting these boards? There are adapter boards available that contain SMA connectors to support the TX->RX cabling shown in your post. Is that what you are doing? If you are trying to do this integration inside a MicroTCA enclosure, it gets more complicated.
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Thank you for your reply Tom,
As I understood I should connect only RX and TX pairs, not clk pair. then connection will be like,
for 2 lane;
6678L Card v1.0 6678L Card v0.3 ----------------- ----------------- 44 AMCC_P4_PCIe_TX1P => 47 AMCC_P4_PCIe_RX1P 45 AMCC_P4_PCIe_TX1N => 48 AMCC_P4_PCIe_RX1N <= 47 AMCC_P4_PCIe_RX1P <= 44 AMCC_P4_PCIe_TX1P 48 AMCC_P4_PCIe_RX1N 45 AMCC_P4_PCIe_TX1N 50 AMCC_P5_PCIe_TX2P => 53 AMCC_P5_PCIe_RX2P 51 AMCC_P5_PCIe_TX2N => 54 AMCC_P5_PCIe_RX2N 53 AMCC_P5_PCIe_RX2P <= 50 AMCC_P5_PCIe_TX2P 54 AMCC_P5_PCIe_RX2N <= 51 AMCC_P5_PCIe_TX2N
+ 5 GND
for 1 lane(with configuring corresponding bit in register in the program)
6678L Card v1.0 6678L Card v0.3 ----------------- ----------------- 44 AMCC_P4_PCIe_TX1P => 47 AMCC_P4_PCIe_RX1P 45 AMCC_P4_PCIe_TX1N => 48 AMCC_P4_PCIe_RX1N
47 AMCC_P4_PCIe_RX1P <= 44 AMCC_P4_PCIe_TX1P
48 AMCC_P4_PCIe_RX1N 45 AMCC_P4_PCIe_TX1N
+ 3 GND
For your question;
we have 2 male connector for AMC edge connector. Initially card will be placed very close may be less than 10mm, therefore we think empedance matching is not required, only cable length will be the same.
In 6678 schematic there are 2 100nf capacitor for AC coupling, we add no AC coupling capacitor.
The port connections are correct. You do not need to add any DC-blocking capacitors since they are on all of the the RX ports adjacent to the DSP for the PCIe lanes.
I am not certain of your connection method. Are you using cables or are you planning to use an adapter board that has 2 male AMC connectors on it? One adapter solution that uses SMA cables can be found at: http://silicontkx.com/SMA-AMCULTRA9000.html. We have successfully used this adapter card.
I believe Goksel is using one of our chassis setups Tom, but for the benefit of everyone reading the thread, I wanted to point out the BOC card availabe on TIeStore...
If you need more help, please reply back. If this answers the question,
please click Verify Answer , below.
Actually we want to connect 6678 to FPGA through PCIe. Before that, we test PCIe connection with 2 6678L. Fast realization, we will connect PCIe pairs with ordinary twisted cable, not a special card. In order to protect card from solder, we make solder to female AMC connector. To avoid empedance matching, we plan to use very short cables(<10mm).
I apologize on my earlier confusion, it was a case of mistaken identity, I mixed you up with someone else doing similar work. Tom can comment here too, but the approach you are taking may not turn out to be the quickest if you end up fighting signal integrity issues. It is definitely not a recommended method for connecting SerDes based interfaces. You may want to consider the BOC mentioned above.
Thank you for your comments.
You say PCIe pins 80/81 does not supply ref. clock. This is true. But why you didn't put PCIe ref clock on AMC edge? How can we work with end point cards that needs external clock to proceed? (For example with XIO2200A EVM). This EVM is working properly when we connect with PCs motherboard but don't work with 6678L card. I think the problem is there is no reference clock source for XIO2200A. Do you have any advice? Some literature says in PCIe clock is embedded in data lines but is 8b/10b encoding such a magical thing? Can endpoints work without reference clock?
SERDES interfaces do not require clock for data transfer and recovery. These high data rates can only be achieved through the integrated Clock-Data recovery at the physical layer. The SERDES interfaces then normally have a local clock source that the data synchronizes into. This local clock is also normally used for the transmit link. Common clock to both ends of the link can also be used such as to support a spread-spectrum clock to reduce EMI radiation. The PCIe interface is defined to work both ways. The C6678 EVM contains a local clock source for the PCIe interface. It also accepts an input clock on the AMC FCLK pins 80 and 81 so that it can be connected to devices, such as ATX PCs, that are using a spread-spectrum PCIe reference clock. The C6678 EVM does not support the option to drive clock out onto these pins.
I am not familiar with the XIO2200A EVM that you mention. If it is an FPGA, I suspect it can use a local oscillator for its PCIe interface. The C6678 EVMs can be connected as shown above in this thread and they communicate successfully where both are running on their own internal local clock. We have also successfully integrated the C6678 EVM into PCIe systems running with a distributed spread-spectrum PCIe clock, such as an ATX PC.
Hi goksel gunlu,
I have the same job as you, and I wonder, is that you managed to make transactions between the two device (FPGA, C6678) by connecting the RX<=> TX by wires?.
We connected two 6678l evm through PCIe succesfully. Since FPGA required clock 100Mhz and 6678L couldn't supply 100MHz reference clock, we couldn't connect FPGA and 6678L. 6678L have two 62005 clock ic and 4 of them is empty. I really wonder why board designer not supplied one of the clock channel to AMC output as PCIe clock.
SERDES interfaces like PCIe are multi-gigabit transmission lines. They need to propagate over carefully managed routes. They are not going to operate correctly over jumper wires. If you wish to connect an FPGA to a DSP with PCIe, you will need to find appropriate adapters and/or cables. Most PCIe capable boards have a PCIe connector or SMA connectors. There are adapters for the DSP to get to SMA connectors from Silicon Turnkey Express. SAMTEC sells cables to bridge from SMA to PCIe. We also sell a PCIe carrier for our EVM to allow it to be plugged into an ATX computer chassis and we sell a Dual-EVM break-out card for connecting 2 cards that each contain AMC edge connectors. These are available at: http://www.ti.com/tool/tmdxevmpci and https://estore.ti.com/CI2EVMBOC--P2685.aspx.
Thanks for your information,
We have this adapter. Our problem is that we did not find a connector PCIe female / female to connect our FPGA and DSP.
I think DSP 6678L could supply 100MHz reference clock.
" The clocks required for clocking data and PHY functional clocks are generated by th e PHY through the supplied input 100 MHz differential clock with no more than 300 ppm tolerance." Manual sprugs6a of TI.
You are quoting the SPRUGS6A out of context. The PCIe User Guide SPRUGS6A is for the PCIe subsystem circuitry contained within the KeyStone DSP. It is not discussing the functionality of the EVM. The full paragraph is copied below:
1.4.4 Clock, Reset, Power Control LogicSeveral clock domains exist within PCIESS. These clocks are functional clocks used bythe PCIe controller and interface bridges as well as receive and transmit clocks used toclock data in and out respectively. The clocks required for clocking data and PHYfunctional clocks are generated by the PHY through the supplied input 100 MHzdifferential clock with no more than 300 ppm tolerance. The PCIe controller functionalclock frequency is generated from the internal PLL and its frequency should be250 MHz.
The C6678 EVM does not output a PCIe clock. It either operates on a local clock or it can accept a clock provided on the FCLK pins.
You can purchase an SMA-to-female-PCIe connector from Samtec at http://www.samtec.com/documents/webfiles/pdf/pcrf.pdf. You can get an AMC to SMA breakout card from http://silicontkx.com/SMA-AMCULTRA9000.html.
The EVM can also be integrated with an FPGA development platform inside a MicroTCA enclosure. There are multiple variations that supply the PCIe clock on the backplane for all modules.
thank's Tom for your information,
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