Our application is initially loaded via PCIe. That means we have a working primary i2c boot, followed by a secondary PCIe boot. The host can then upload the software to the DSP and run it. That works fine.
However, the host initiated reset is a problem. The host has GPIO connected pins to the reset inputs (soft, hard (RESETFULL) and local resets but we cannot use POR because that is shared between different components on our board!) of the DSP.
After reset is given, the DSP is expected to rerun the bootloader and follow the exact same sequence as on a POR except for polling the DEVSTAT register pins. After the host has restored the PCIe configuration of the DSP, I can again upload software (and write/read registers across PCIe) to the DSP, but this newly uploaded software never runs.
In another thread, I read that someone was able to reset the DSP via PCIe commands (although not recommended or supported because of PLL issues). I also succeeded in doing just that: resetting (soft reset or hard reset) the DSP by just writing registers across PCIe but the outcome is the same. After reset, I can upload new software, but it does not run.
What is missing here?
Or has the DSP not come out of reset correctly?
Is the POR required for this feature?
Hi Gert, I think that old thread was started by me.
We are able to reset over PCIe by writing to the PLL Reset register, and we do this all the time.
You must do this:
Enable MST_PRIV bit in PCIE_PRIORITY_REG from the host (otherwise key below wont be accepted and nothing will happen).
Write the proper key value (0x5A69 i think) to the PLL_RSTCNTL register. Check that the key was accepted, by reading back, I think it should be 0x000C. This step can easily go wrong.
Request the reset via PL_RSTCNTL register.
After the reset, I suggest connecting to the C6678 using CCS, and check that Core 0 has re-entered the IBL (probably addresses 0x00800000 to 0x0081FFFF) and is polling the Boot Magic Address.
Best wishes, Jonathan
Hi Jonathan,
yes, I read your great tip about PCIe host driven reset.
To clarify my question:
Reset is working.
In short the local DSP procedure is...
volatile unsigned int* pE8 = (volatile unsigned int*) (0x023100E8);
volatile unsigned int* pEC = (volatile unsigned int*) (0x023100EC);
volatile unsigned int nE8 = *pE8;
volatile unsigned int Key = 0x5A69;
*pE8 = Key;
*pEC |= ((1 << 12) | (1 << 13)); // set as soft reset, standard would be hard reset
*pE8 = 0; // reset
To summarize, in order to enable MST, via PCIe...
unsigned int* p_mapped points to the TI DSP 4K config section.
and #define TI_PCIE_PRIORITY 0x3C //3Ch Section 3.1.14
volatile unsigned int* pRegister;
if (do_enableprivilege)
{ // this enables privileged writes initiated by PCIe
unsigned int bit = (0x1<<16);
pRegister = (unsigned int *) ( ((unsigned int) p_mapped) + TI_PCIE_PRIORITY);
*pRegister = SWAP(bit); // Big endian host to Little endian DSP
}
After, that the 0x02310000 registers can be mapped via PCIe and the same procedure as the local running reset function can be performed.
I checked and IBL is restarted at PC 0x20B00000, both for local running reset, or PCIe remotely triggered reset.
The same thing happens when the (not POR) reset pins are toggled. However, in both cases the software upload procedure has not the desired outcome.
PCIe seems to be OK after the reset: I can peek and poke memory in the DSP from the host. Upload is working; I need to verify whether it starts (as triggered by Host) or not. So, I will need to debug that further and check whether it leaves the IBL and attempts to run the uploaded software.
I was just wondering what could prevent the software from running again, especially taking into account that the upload procedure works the first time.
following experiment done:
Note: The programmed magic boot address for core 0 was correct and was thus 0x10800000.
The code snippet to get the DSP out of reset is as follows:
/* Now poke the legacy interrupt on the EP to have it break out of boot. Do it twice just to be sure */ if (do_prints) printf("set registers... trigger INT\n"); pRegister = (unsigned int *) ( ((unsigned int) p_mapped) + TI_MSI_IRQ); *pRegister = SWAP(0xff00); /* This register is written to by the remote device. Writes initiated by an EP over PCIe link that target BAR0 of the RC land to this register if the offset matches. To generate MSI Interrupt 0, the EP should write 0x0000_0000 to this register. It will result in a pulse on bit zero triggering the MSI interrupt from PCIESS to the external processor. */ if (do_prints) printf("set registers... trigger INT..DONE1\n"); *pRegister = SWAP(0xff00); if (do_prints) printf("set registers... trigger INT..DONE2\n");My current work hypothesis is that the IBL is not triggered correctly to start the program at the magic_boot_address.
Are you using RESETFULL or RESETZ. You need either RESETFULL or POR to trigger the complete boot loader process.
Thanks,
Arun.
If you need more help, please reply back. If this answers the question, please click Verify Answer , below.
RESETFULL is used.
Best regards,
Gert.
Are you still poking the boot magic address and sending the MSI interrupts after you load the program right?
thanks,
Arun
Yes, exact same procedure as on a first-time upload.
This is strange. Where is the PC after you loaded the program through PCIe? Also see if there is the devstat register value is different between the two cases.
arun
Gert,
One more thing to mention is the that only the sticky bits in the PCIe memory-mapped registers (MMRs) will be retained (most of them will be reset to default values) after the soft reset (RESETFULL). The description in the data manuals will be revised in the next release.
That means you need to re-program the applications registers (e.g. address translation, interrupt setup) and configuration registers (e.g. BARs) after the reset.
So you should check if the host could indeed trigger the MSI interrupt in PCIe and wake up the Core0 for boot_magic_address.
Sincerely,
Steven
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Please click the Verify Answer button on this post if it answers your question.
There is indeed a difference between the interrupt registers on a first and second software upload. Considering the order in the boot process: first I2C, then PCIe, then the IBL waits for the interrupt + magic boot address. Should the IBL not have set the interrupt registers in the correct state?
I will now try to manually set the registers in the same state as on a first upload, then check whether the interrupt can be triggered and whether the IBL transfers the PC to the magic boot address.
I reprogrammed the interrupt registers so that they are identical to a first upload status; but to no avail.
According to SPRUGY5A—September 2011, page 28:
"If the I2C EEPROM is used to configure the PCI registers, the BAR configurations aredriven by the parameter table downloaded through I2C. On the boot reentry, the PCIeboot code is executed with these BAR configurations. In this mode of operation, the I2Cperipheral is also configured by the bootloader.The bootloader code also configures the interrupt subsystem by configuring thechip-level interrupt controller, then executes the IDLE instruction (Mostly MSI orlegacy interrupts can be used). After the host transfers the boot table directly to thememory location and if the BOOT MAGIC ADDRESS register is non-zero, the ROMcode copies the start address of the application from the BOOT MAGIC ADDRESS tothe program counter wakes up the DSP through an interrupt generated by poking theMSI application register and executes the application loaded. If the BOOT MAGICADDRESS register is still zero the ROM code keeps the DSP in idle till the value isnon-zero."
So the IBL configures the interrupt subsystem? That clearly has not happened here. Am I looking at a real reset problem?
DEVSTAT register reads in both scenarios 0x0001000B
Can I force a local reset on core 0 to start software at L2SRAM?
I have a question for you: Are uploading your software via PCIe or are you using e.g. FLASH ?
Hi All, :-)
I have here the register dump taken at the time right after the second software upload (after the reset).
IBL code is running PC@0x20B01270, which is disassembled into the 'IDLE' instruction.
What we don't know is whether the I2C part has run to completion. The I2C part initializes the DDR3 RAM and performs the PLL fix.
I can read/write the DDR3 RAM via PCIe at this stage. So, it seems I2C did run. Then IBL PCIe initialization should have been performed.
Since the host can talk to the DSP via PCIe, this probably has also run.
Core Registers Core Registers PC 0x20B01270 Core Register CLK 0x00000000 Core Register SP 0x0087FFA0 Core Register FP 0x0087FFA0 Core Register A0 0x00000001 Core Register A1 0x00000001 Core Register A2 0x01000000 Core Register A3 0x01000000 Core Register A4 0x01845044 Core Register A5 0x20000000 Core Register A6 0x00000018 Core Register A7 0x00000000 Core Register A8 0x21800004 Core Register A9 0x20B09A80 Core Register A10 0x000003F0 Core Register A11 0x0087FFFC Core Register A12 0x02320010 Core Register A13 0x00873700 Core Register A14 0x00873680 Core Register A15 0x008734A8 Core Register A16 0x00000000 Core Register A17 0x002625A0 Core Register A18 0x0002625A Core Register A19 0x00000000 Core Register A20 0x00000000 Core Register A21 0x00EE6B28 Core Register A22 0x00873680 Core Register A23 0x0040202C Core Register A24 0x00000010 Core Register A25 0x0081D5CC Core Register A26 0x0081D5CC Core Register A27 0x00000001 Core Register A28 0x00000000 Core Register A29 0x0081EFCC Core Register A30 0x00000001 Core Register A31 0x00000000 Core Register B0 0x21000001 Core Register B1 0x20000001 Core Register B2 0x00000000 Core Register B3 0x20B01264 Core Register B4 0x02620140 Core Register B5 0x20B00000 Core Register B6 0x20B00FAC Core Register B7 0x21800004 Core Register B8 0x80000000 Core Register B9 0x21800004 Core Register B10 0x02320018 Core Register B11 0x0262003C Core Register B12 0x02310100 Core Register B13 0x0000006A Core Register B14 0x00800E3C Core Register B15 0x0087FFA0 Core Register B16 0x0016E35F Core Register B17 0x0087319C Core Register B18 0x00000181 Core Register B19 0x0000000E Core Register B20 0x00000000 Core Register B21 0x3000B000 Core Register B22 0x22000008 Core Register B23 0x12280110 Core Register B24 0x01000423 Core Register B25 0x05044684 Core Register B26 0x38EA5601 Core Register B27 0x04031000 Core Register B28 0xC0AC0000 Core Register B29 0x800A0103 Core Register B30 0x0081D5CC Core Register B31 0x00000031 Core Register AMR 0x00000000 Core Register: Addressing mode register _RESV 0x0 Reserved BK1 0x0 Block size 1 BK0 0x0 Block size 0 B7MODE 0x0 - LINEAR B7 mode B6MODE 0x0 - LINEAR B6 mode B5MODE 0x0 - LINEAR B5 mode B4MODE 0x0 - LINEAR B4 mode A7MODE 0x0 - LINEAR A7 mode A6MODE 0x0 - LINEAR A6 mode A5MODE 0x0 - LINEAR A5 mode A4MODE 0x0 - LINEAR A4 mode CSR 0x15000103 Core Register: Control status register CPU_ID 0x15 CPU ID REV_ID 0x00 Revision ID PWRD 0x0 Control power-down modes SAT 0x0 - NONSATURATE Saturate EN 0x1 - LITTLE Endianness PCC 0x0 Program Cache control mode DCC 0x0 Data Cache control mode PGIE 0x1 Previous GIE GIE 0x1 - ENABLE Global interrupt enable IFR 0x00000000 Core Register: Interrupt Flag Register _RESV **************** Reserved IF15 0x0 Interrupt flag 15 IF14 0x0 Interrupt flag 14 IF13 0x0 Interrupt flag 13 IF12 0x0 Interrupt flag 12 IF11 0x0 Interrupt flag 11 IF10 0x0 Interrupt flag 10 IF9 0x0 Interrupt flag 9 IF8 0x0 Interrupt flag 8 IF7 0x0 Interrupt flag 7 IF6 0x0 Interrupt flag 6 IF5 0x0 Interrupt flag 5 IF4 0x0 Interrupt flag 4 _RESV ** Reserved NMIF 0x0 Non maskable Interrupt flag _RESV * Reserved ISR 0x00000000 Core Register: Interrupt Set Register _RESV 0x0000 Reserved IS15 0x0 Interrupt 15 Set IS14 0x0 Interrupt 14 Set IS13 0x0 Interrupt 15 Set IS12 0x0 Interrupt 14 Set IS11 0x0 Interrupt 15 Set IS10 0x0 Interrupt 14 Set IS9 0x0 Interrupt 15 Set IS8 0x0 Interrupt 14 Set IS7 0x0 Interrupt 15 Set IS6 0x0 Interrupt 14 Set IS5 0x0 Interrupt 15 Set IS4 0x0 Interrupt 15 Set _RESV **** Reserved ICR 0x00000000 Core Register: Interrupt clear Register _RESV 0x0000 Reserved IC15 0x0 Interrupt 15 Clear IC14 0x0 Interrupt 14 Clear IC13 0x0 Interrupt 15 Clear IC12 0x0 Interrupt 14 Clear IC11 0x0 Interrupt 15 Clear IC10 0x0 Interrupt 14 Clear IC9 0x0 Interrupt 15 Clear IC8 0x0 Interrupt 14 Clear IC7 0x0 Interrupt 15 Clear IC6 0x0 Interrupt 14 Clear IC5 0x0 Interrupt 15 Clear IC4 0x0 Interrupt 14 Clear _RESV **** Reserved IER 0x000003F3 Core Register: Interrupt enable Register _RESV **************** Reserved IE15 0x0 - DISABLE Interrupt enable 15 IE14 0x0 - DISABLE Interrupt enable 14 IE13 0x0 - DISABLE Interrupt enable 13 IE12 0x0 - DISABLE Interrupt enable 12 IE11 0x0 - DISABLE Interrupt enable 11 IE10 0x0 - DISABLE Interrupt enable 10 IE09 0x1 - ENABLE Interrupt enable 9 IE08 0x1 - ENABLE Interrupt enable 8 IE07 0x1 - ENABLE Interrupt enable 7 IE06 0x1 - ENABLE Interrupt enable 6 IE05 0x1 - ENABLE Interrupt enable 5 IE04 0x1 - ENABLE Interrupt enable 4 _RESV ** Reserved NMI 0x1 Non maskable interrupt Reserved * ISTP 0x20B0FC00 Core Register: Interrupt service table pointer ISTB 0x82C3F Interrupt Service table base address HPEINT 0x0 Specific interrupt occurred _RESV 0x0 Reserved IRP 0x20B01274 Core Register: Interrupt return pointer NRP 0x00000000 Core Register: Non maskable interrupt ERP 0x00000000 Core Register: Exception return pointer TSCL 0x00000000 Core Register: Low half of 64-bit timestamp TSCH 0x00000000 Core Register: High half of 64-bit timestamp ARP 0x00000000 Core Register: Analysis return pointer ILC 0x00000000 Core Register: Inner loop SPL buffer count RILC 0x00000000 Core Register: Reload Inner loop SPL buffer count PCE1 0x20B01270 Core Register: Program counter E1 phase DNUM 0x00000000 Core Register: DSP Number _RESV 0x000000 Reserved DSPNUM 0x00 FADCR 0x00000000 Core Register: Floating Point Register FAUCR 0x00000000 Core Register: Floating Point Register FMCR 0x00000000 Core Register: Floating Point Register SSR 0x00000000 Core Register: Saturation status register RESV 0x000000 Reserved M2 0x0 Saturation in M2 Unit M1 0x0 Saturation in M1 Unit S2 0x0 Saturation in S2 Unit S1 0x0 Saturation in S1 Unit L2 0x0 Saturation in L2 Unit L1 0x0 Saturation in L1 Unit GPLYA 0x00000000 Core Register: GMPY polynomial for A-side GPLYB 0x00000000 Core Register: GMPY polynomial for B-side GFPGFR 0x0700001D Core Register: Galois field multiply control register _RESV 0x0 Reserved SIZE 0x7 Size _RESV 0x0000 Reserved POLY 0x1D Polynomial DIER 0x00000000 Core Register: Debug interrupt enable register TSR 0x00000001 Core Register: Task state register _RESV 0x0000 Reserved IB 0x0 - UNBLOCKED Interrupts blocked SPLX 0x0 - NOTEXEC SPLOOP Executing _RESV 0x0 Reserved EXC 0x0 - NOTEXEC Execption Processing INT 0x0 - NOTEXEC Interrupt Processing _RESV 0x0 Reserved CXM 0x0 - SUPERVISOR Current Execution Mode _RESV 0x0 Reserved DBGM 0x0 - EMU_ENABLE Emulator debug mask XEN 0x0 - DISABLE Maskable exception enable GEE 0x0 - DISABLE Globale exception enable SGIE 0x0 Saved global interrupt enable GIE 0x1 - ENABLE Global interrupt enable ITSR 0x00000001 Core Register: Interrupt task state register _RESV 0x0000 Reserved IB 0x0 - UNBLOCKED Interrupts blocked SPLX 0x0 - NOTEXEC SPLOOP Executing _RESV 0x0 Reserved EXC 0x0 - NOTEXEC Execption Processing INT 0x0 - NOTEXEC Interrupt Processing _RESV 0x0 Reserved CXM 0x0 - SUPERVISOR Current Execution Mode _RESV 0x0 Reserved DBGM 0x0 - EMU_ENABLE Emulator debug mask XEN 0x0 - DISABLE Maskable exception enable GEE 0x0 - DISABLE Globale exception enable SGIE 0x0 Saved global interrupt enable GIE 0x1 - ENABLE Global interrupt enable NTSR 0x00010000 Core Register: Non maskable TSR snapshot _RESV 0x0001 Reserved IB 0x0 - UNBLOCKED Interrupts blocked SPLX 0x0 - NOTEXEC SPLOOP Executing _RESV 0x0 Reserved EXC 0x0 - NOTEXEC Execption Processing INT 0x0 - NOTEXEC Interrupt Processing _RESV 0x0 Reserved CXM 0x0 - SUPERVISOR Current Execution Mode _RESV 0x0 Reserved DBGM 0x0 - EMU_ENABLE Emulator debug mask XEN 0x0 - DISABLE Maskable exception enable GEE 0x0 - DISABLE Globale exception enable SGIE 0x0 Saved global interrupt enable GIE 0x0 - DISABLE Global interrupt enable ETSR 0x00010000 Core Register: Exception TSR snapshot _RESV 0x0001 Reserved IB 0x0 Interrupts blocked SPLX 0x0 SPLOOP Executing _RESV 0x0 Reserved EXC 0x0 Execption Processing INT 0x0 Interrupt Processing _RESV 0x0 Reserved CXM 0x0 Current Execution Mode _RESV 0x0 Reserved DBGM 0x0 Emulator debug mask XEN 0x0 Maskable exception enable GEE 0x0 Globale exception enable SGIE 0x0 Saved global interrupt enable GIE 0x0 Global interrupt enable EFR 0x00000000 Core Register: Exception Flag Register NXF 0x0 NMI Exception flag EXF 0x0 EXCEP Exception flag _RESV 0x0000000 Reserved IXF 0x0 Internal Exception flag OXF 0x0 OSSR Exception flag ECR 0x00000000 Core Register: Exception clear register NXC 0x0 NMI Exception Clear EXC 0x0 EXCEP Exception Clear _RESV 0x0000000 Reserved IXC 0x0 Internal Exception Clear OXC 0x0 OSSR Exception Clear IERR 0x00000000 Core Register: Internal exception cause register RegisterPairs RegisterPairs A1_A0 0x0000000100000001 Core Register A3_A2 0x0100000001000000 Core Register A5_A4 0x2000000001845044 Core Register A7_A6 0x0000000000000018 Core Register A9_A8 0x20B09A8021800004 Core Register A11_A10 0x0087FFFC000003F0 Core Register A13_A12 0x0087370002320010 Core Register A15_A14 0x008734A800873680 Core Register A17_A16 0x002625A000000000 Core Register A19_A18 0x000000000002625A Core Register A21_A20 0x00EE6B2800000000 Core Register A23_A22 0x0040202C00873680 Core Register A25_A24 0x0081D5CC00000010 Core Register A27_A26 0x000000010081D5CC Core Register A29_A28 0x0081EFCC00000000 Core Register A31_A30 0x0000000000000001 Core Register B1_B0 0x2000000121000001 Core Register B3_B2 0x20B0126400000000 Core Register B5_B4 0x20B0000002620140 Core Register B7_B6 0x2180000420B00FAC Core Register B9_B8 0x2180000480000000 Core Register B11_B10 0x0262003C02320018 Core Register B13_B12 0x0000006A02310100 Core Register B15_B14 0x0087FFA000800E3C Core Register B17_B16 0x0087319C0016E35F Core Register B19_B18 0x0000000E00000181 Core Register B21_B20 0x3000B00000000000 Core Register B23_B22 0x1228011022000008 Core Register B25_B24 0x0504468401000423 Core Register B27_B26 0x0403100038EA5601 Core Register B29_B28 0x800A0103C0AC0000 Core Register B31_B30 0x000000310081D5CC Core Register
The config space registers read out:
dumping regs------------read register 0x00000000, value 0x4e301100read register 0x00000004, value 0x00000005read register 0x00000008, value 0x00000000read register 0x0000000c, value 0x00000000read register 0x00000010, value 0x00000000read register 0x00000014, value 0x00010000read register 0x00000020, value 0x00000000read register 0x00000024, value 0x00000000read register 0x00000028, value 0x00000000read register 0x00000030, value 0x00000000read register 0x00000034, value 0x00000000read register 0x00000038, value 0x00000000read register 0x0000003c, value 0x00000000read register 0x00000050, value 0x00000000read register 0x00000054, value 0x00000000read register 0x00000064, value 0x00000000read register 0x00000068, value 0x00000000read register 0x0000006c, value 0x00000000read register 0x00000070, value 0x00000000read register 0x00000074, value 0x00000000read register 0x00000078, value 0x00000000read register 0x0000007c, value 0x00000000read register 0x00000100, value 0x00000000read register 0x00000104, value 0x00000000read register 0x00000108, value 0x00000001read register 0x0000010c, value 0x00000001read register 0x00000110, value 0x00000000read register 0x00000114, value 0x00000000read register 0x00000118, value 0x00000000read register 0x0000011c, value 0x00000000read register 0x00000120, value 0x00000000read register 0x00000124, value 0x00000000read register 0x00000128, value 0x00000000read register 0x0000012c, value 0x00000000read register 0x00000130, value 0x00000000read register 0x00000134, value 0x00000000read register 0x00000138, value 0x00000000read register 0x0000013c, value 0x00000000read register 0x00000140, value 0x00000000read register 0x00000144, value 0x00000000read register 0x00000148, value 0x00000000read register 0x0000014c, value 0x00000000read register 0x00000150, value 0x00000000read register 0x00000154, value 0x00000000read register 0x00000158, value 0x00000000read register 0x0000015c, value 0x00000000read register 0x00000160, value 0x00000000read register 0x00000164, value 0x00000000read register 0x00000168, value 0x00000000read register 0x0000016c, value 0x00000000read register 0x00000170, value 0x00000008read register 0x00000174, value 0x00000000read register 0x00000178, value 0x00000000read register 0x0000017c, value 0x00000000read register 0x00000180, value 0x00000000read register 0x00000184, value 0x00000000read register 0x00000188, value 0x00000001read register 0x0000018c, value 0x00000001read register 0x00000190, value 0x00000000read register 0x00000194, value 0x00000000read register 0x00000198, value 0x00000001read register 0x0000019c, value 0x00000001read register 0x000001a0, value 0x00000000read register 0x000001a4, value 0x00000000read register 0x000001a8, value 0x00000001read register 0x000001ac, value 0x00000001read register 0x000001b0, value 0x00000000read register 0x000001b4, value 0x00000000read register 0x000001b8, value 0x00000001read register 0x000001bc, value 0x00000001read register 0x000001c0, value 0x00000000read register 0x000001c4, value 0x00000000read register 0x000001c8, value 0x00000000read register 0x000001cc, value 0x00000000read register 0x000001d0, value 0x00000000read register 0x000001d4, value 0x00000000read register 0x000001d8, value 0x00000000read register 0x000001dc, value 0x00000000read register 0x00000300, value 0x00000001read register 0x00000304, value 0xca400000read register 0x00000308, value 0x00000000read register 0x0000030c, value 0x10800000read register 0x00000310, value 0x00000002read register 0x00000314, value 0x11800000read register 0x00000318, value 0x00000000read register 0x0000031c, value 0x00000000read register 0x00000320, value 0x00000003read register 0x00000324, value 0x12800000read register 0x00000328, value 0x00000000read register 0x0000032c, value 0x00000000read register 0x00000330, value 0x00000004read register 0x00000334, value 0x80000000read register 0x00000338, value 0x00000000read register 0x0000033c, value 0x00000000read register 0x00000380, value 0x00002110read register 0x00000384, value 0x00000000read register 0x00000388, value 0x00001333read register 0x00000390, value 0x000622a0read register 0x00000394, value 0x000222a0------------
Based on the dump of PCIe registers, it looks like the MSI0 is enabled (MSI0_IRQ_ENABLE_SET (0x108)=1), but there is no MSI0 interrupt being triggered (MSI0_IRQ_STATUS_RAW (0x100) = 0). Instead, the MSI7 status register has some bit being set as MSI7_IRQ_STATUS_RAW (0x170) = 0x8. It may raise the question that if the MSI0 interrupt is really being triggered in the second time (after reset).
I am not sure what the "SWAP(0xff00)" is doing in the following code section you mentioned before. Could you double check if the MSI0 is actually being triggered (write 0x0 to MSI_IRQ (0x54)) please?
/* Now poke the legacy interrupt on the EP to have it break out of boot. Do it twice just to be sure */ if (do_prints) printf("set registers... trigger INT\n"); pRegister = (unsigned int *) ( ((unsigned int) p_mapped) + TI_MSI_IRQ); *pRegister = SWAP(0xff00); /* This register is written to by the remote device. Writes initiated by an EP over PCIe link that target BAR0 of the RC land to this register if the offset matches. To generate MSI Interrupt 0, the EP should write 0x0000_0000 to this register. It will result in a pulse on bit zero triggering the MSI interrupt from PCIESS to the external processor. */ if (do_prints) printf("set registers... trigger INT..DONE1\n"); *pRegister = SWAP(0xff00); if (do_prints) printf("set registers... trigger INT..DONE2\n");
Hi Steven,
I double-checked and write 0x00000000 twice to MSI_IRQ (0x54). The same outcome.
Br,
Hi Gert, sorry for the delay, I've been out of office, working on other stuff, etc.
I am loading over PCIe.
We use R1.0 Silicon C6678 on EVM board, with the PLL workaround. So the C6678 first loads the PLL workaround from I2C, then configures PCIe and waits for the Root Complex to download software and set Boot Magic Address.
The version of the PLL workaround bootloader that we use does not expect an MSI interrupt. It just sits in a loop reading the boot magic address until it is non-zero.
We also do the same thing on some boards we built ourself (some with R1.0 silicon, some with R2.0), but in both cases using the PLL workaround first loaded from I2C then load over PCIe with Boot Magic Address set by RC.
We are just starting to experiment with R2.0 silicon without the PLL workaround (because not needed with R2.0), direct boot purely from the ROM boot loader over PCIe.
In that case, I notice the behavior is a bit different. The RC host has to write the Boot Magic Address, then send an MSI interrupt (data 0 to DSP address 0x21800054).
I did notice that if the MSI is sent while Boot Magic Adress is still zero, the C6678 seems to lock up and ignore any later MSI that is sent after setting boot magic address.
So it's important to set magic address on Core 0 (and read it back to flush the write buffers) before sending any MSI.
That's as far as I've got, and am working on something more urgent right now.
Regards, Jonathan