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The two CDCE62005 clock generators are currently used to generate six possible clock inputs to the C6678.  There are a number of issues to consider if you were switching to the  CDCE72010 and I can't say whether it would work for you application without additional details on what you're trying to accomplish.  It's clear that you would have to add an external VCXO and it's appropriate circuitry to use the CDCE72010 and calculate whether all the frequencies you need could be divided down from a single synthesized frequency.  This couldn't be accomplished for the EVM but that depended, in large part, on the frequencies that we selected for some of the clock inputs.  Remember that we are trying to create an evaluation board that is as flexible as possible and that adds some complexity that you might not need.  For example, both the CORE_CLK and the PA_SS_CLK have 100MHz clock sources, the CORE_CLK from the first CECE62005 and the PA_SS_CLK is from the second.  This was done to provide the possibility of a different clock frequencies for these two inputs but in a real application if both inputs needed 100MHz the PACLKSEL pins could be pulled low allowing the CORE_CLK input to be used by the PA PLL and eliminating the need for a clock on the PA_SS_CLK input. 

What are the clock requirements for you application board?  Are you using all of the SERDES interfaces?  Can you use the same generated clock for the serdes clock inputs by using a clock distribution as opposed to generating each individually?  All these questions need to be answered before determining you clock generator needs.