The C6678 EVB uses 2x CDCE62005 which has 5 differential output clocks each. I am intending to use 1x CDCE72010 which has 10 output clocks.
However, the CDCE62005 and CDCE72010 seems a bit different. CDCE72010 is a Ten Output High Performance Clock Synchronizer, Jitter Cleaner and Clock Distributor whereas CDCE62005 is a Five/Ten Output Clock Generator/ Jitter Cleaner With Integrated Dual VCOs.
Could I replace 2x CDCE62005 with 1x CDCE72010 just like that. My concern is that I may lose some functionality if I switch from CDCE62005 to CDCE72010 (such as the Integrate VCO in CDCE62005 which is not mentioned in CDCE72010).
The two CDCE62005 clock generators are currently used to generate six possible clock inputs to the C6678. There are a number of issues to consider if you were switching to the CDCE72010 and I can't say whether it would work for you application without additional details on what you're trying to accomplish. It's clear that you would have to add an external VCXO and it's appropriate circuitry to use the CDCE72010 and calculate whether all the frequencies you need could be divided down from a single synthesized frequency. This couldn't be accomplished for the EVM but that depended, in large part, on the frequencies that we selected for some of the clock inputs. Remember that we are trying to create an evaluation board that is as flexible as possible and that adds some complexity that you might not need. For example, both the CORE_CLK and the PA_SS_CLK have 100MHz clock sources, the CORE_CLK from the first CECE62005 and the PA_SS_CLK is from the second. This was done to provide the possibility of a different clock frequencies for these two inputs but in a real application if both inputs needed 100MHz the PACLKSEL pins could be pulled low allowing the CORE_CLK input to be used by the PA PLL and eliminating the need for a clock on the PA_SS_CLK input.
What are the clock requirements for you application board? Are you using all of the SERDES interfaces? Can you use the same generated clock for the serdes clock inputs by using a clock distribution as opposed to generating each individually? All these questions need to be answered before determining you clock generator needs.
If you need more help, please reply back. If your question is answered, please click Verify Answer
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.