TI E2E Community
Digital Signal Processors (DSP)
C6000 Multicore DSP
Keystone Multicore Forum (C66, 66A, AM5)
DDR3 Layout with Shannon
Is it possible to place Shannon DSP on CS (Component side) but all its DDR3 memories (4 chips of x16) on PS (Print side)?
We have had customers succesfully place SDRAM components on both the component side and the solder side of boards. The biggest problem with placing the memories on the solder side concerns the added stub associated with the second via for the data lines. Generally if both the memories and the C6678 are on the component side, the data lines will escape from the C6678 on the top layer and drop with a via to a layer close to the bottom. The trace would travel on that layer, always adjacent to a solid ground plane, until it came to the point where the second via would bring the signal back to the top layer for a short route to the ball of the memory component. Since there are only two vias and since the trace is routed on a layer close to the bottom, the via stub from that layer to the bottom of the board is fairly small for both vias. In your case the memories are on the bottom layer. In that scenario most of the length of the second via would be stub since the signal would be traveling from the inner layer to the bottom of the board instead of the top. This stub may cause reflections that could interfere with the operation of you DDR3 interface. There isn't an easy answer to this question. If you're going to place your memories on the bottom you should simulate your data bus to see if the stubs on the data lines will cause any problems.
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Thank you for your reply!
So I understand that the only way to go is by simulating.
1. If simulating shows a problem with this stub caused by via, what could be done? one solution (I think) would be to use blind vias (via from Print-side to the inner routing layer only). This solution could add more cost to PCB. Are there any alternative solutions?
2. If I understand correctly, same problem of stubs would occur with all DDR3 signals (and not only with data lines), correct?
Blind vias would be an effective method of eliminating the stubs in you situation but it would add cost to the board. There are a couple of things you could try to reduce the effects of the stubs. One would be back drilling the stub portion of the via to eliminate the stub. A second method would be to route the data lines closer to the center of the board. This would add a stub length at each of the vias but shorten the stubs. This should change the frequency effected by the stub.
Stubs on the address and command lines are less of a problem. The flyby nature of the routing for these signals already adds the expectation that there will be stubs on the lines. In addition the address and command are toggling at half of the frequency of the data lines so the timing isn't as tight.
Thank you Bill!
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