• Resolved

Hyperlink boot address mappings?

Hi,

The Bootloader user guide (spruggy5a) states:


HyperLink boot code initializes the chip-level interrupt controller to interrupt the DSP
after the boot. After setting up the interrupt configuration, the boot ROM executes an
idle instruction. The remote device loads the memory directly and generates the
HyperLink interrupt. When the boot code is awoken, the interrupt maps are restored
to their default values and the DSP branches to the address in DSP BOOT MAGIC
address. As with PCI, if the value in DSP BOOT MAGIC address is still 0 after wakeup,
the ROM again executes an idle.
HyperLink mapping can be configured by the master, but the bootloader sets up the
initial mappings.

But no information is given about what the actual HyperLink mapping setup is.  Where can I find this info?

Thanks,

Joel
  • Anyone know where this information might be located?

  • In reply to Joel Keller:

    Joel,

    We will add it in the next document version. The table is below.

    Boot ROM Initialized HyperLink Segment Mapping

    Segment

    Size

    Translated Address

    Description

    0 - N

    Size of L2

    Global address of Core0 L2 to CoreN L2

    Global L2

    N + 1

    128k

    0x08000000

    XMC config

    N + 2

    1Mb

    0x0bc00000

    MSMC config

    N + 3

    Size of MSMC memory

    0x0c000000

    MSMC memory

    N + 4

    4Mb

    0x01c00000

    Config Regs

    N + 5

    4Mb

    0x02000000

    Config Regs

    N + 6

    4Mb

    0x02400000

    Config Regs

    N + 7

    2Mb

    0x02800000

    Config Regs

    N + 8

    512 Bytes

    0x21000000

    DDR Config

    (N + 9) – 63

    4Mb

    0x80000000 (4Mb steps)

    DDR Memory

    N - Total number of cores. Check the data manual for the varying sizes.

    Thanks,

    Arun.

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

  • In reply to ArunMani:

    Excellent.  Thanks Arun!