Hi all,
I have one question concerning the input clocks to the TI C6672 DSP. In our design we use one CDCE62005 to generate all necessary clocks. My first idea was to use the
same frequencies as used on the TI C6678 Evaluation Board which are:
CDCE62005 input frequency is 25 MHz
DDR_CLK = 66.67 MHz
PCI_CLK = 100 MHz
SGMII_CLK = 312.5MHz
Core_CLK = 100 MHZ
Now I found out that the CDCE62005 cannot generate this frequency configutation, Advantech I think uses 2 of the CDCE 62005 to solve this.
My question is now if the following input frequency which could be generated by the CDCE62005 will work with the DSP
DDR_CLK = 200 MHz
SGMII_CLK = 250MHz
CoreCLK = 100 MHz
Thx for your help
I think you can generate the frequencies you've listed but it would probably require fewer changes to the software if you used the following.
DDRCLK = 66.67MHz
PCICLK = 100MHz
SRIOSGMIICLK = 250MHz
CORECLK = 100MHz
The CDCE62005 can generate all of these clocks from the 25Mhz input clock. Note that all the SERDES interfaces are designed to accept 156.25MHz, 250MHz and 312.5MHz as a reference clock while the PCIECLK can also accept 100MHz allow the use of the standard PCIE backplane clock input. The only difference between these frequencies is the multiplier values in the serdes PLL and the allowable jitter on the input reference clock. Since the jitter is multiplied along with the clock the lower reference clock frequencies must be cleaner. Since you are generating the PCIECLK with the CDCE62005 you may want to consider using 250MHz to take advantage of this fact.
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Hi Bill,
thanks for your answer, but I dont really understand your last sentence, do you mean to use 250 MHZ for PCI Clock ?
The PCIE reference clock, PCIECLKP/N, can be one of four specific frequencies. These are 100MHz, 156.25MHz, 250MHz and 312.5MHz. Any of these four frequencies can be used by the PLL in the PCIE subsystem to generate the correct timing for a PCIE connection. The PCIE spec allows the root complex and the endpoints to use a different reference clock as long as none of them are using spread spectrum clocking. Do you know the clocking of the other devices on the PCIE interface?
Let me make a correction to my earlier post. The CDCE62005 does not have the ability to create 250MHz, 100MHz and 66.67MHz. That doesn't prevent you from using a single CDCE62005 as a clock source for your design. You can generate 250Mhz, 100MHz and 50MHz and connect the later to the DDRCLKP/N. The internal PLL for the DDR3 interface can use the 50MHz to generate the 66.67MHz clock needed by the DDR.
I noticed you never input clk for Hyperlink clk and PASS clk. Is it that the interfaces are not used, hence the input clk can be not provided. May I know what is the PASS used for? Is it for Ethernet interface?
The original question from Markus was specific to his design. If the Hyperlink interface isn't used then the MCMCLKP/N inputs can be tied off as described in the Hardware Design Guide. The clock for the PASS PLL can come from either the PASSCLKP/N inputs or the CORECLKP/N inputs. This selection is controlled with the PACLKSEL configuration input. See the PASS PLL section (7.7) of the data manual for more detail. The PASS PLL provides the clock for the Network Coprocessor which consists of the the Packet DMA controller, the Packet Accelerator, the Security Accelerator and the Gigabit Ethernet Switch Subsystem. Note that the SerDes for the SGMII interfaces do not use this clock. They use the SRIOSGMIICLKP/N inputs as their clock source. If you use the CORECLKP/N inputs as a clock source for the PASS PLL then the PASSCLKP/N inputs may be tied off as described in the Hardware Design Guide.
Understand. The PASS is for Network coprocessor which has Packet DMA controller, Packet Accelerator, Security Accelerator and the Gigabit Ethernet Switch Subsystem.
May I know what is the role for each? Is all of them special features of the Ethernet interface, meaning if I just want to use Ethernet interface to transmit data to another processor, I do not need the special features, hence I do not need to clock the PASS_PLL?
For the Gigabit Ethernet Switch subsystem, is the c66 acting as a switch, meaning it switches data from SGMII0 to SGMII1?
There are users guides for each of these subsystems that describe the functionality and provide programming information on the website for the C6672. They are all associated with the packet interface and are designed to optimize the movement of packets. This subsystem include the Gigabit Ethernet Switch which is necessary for moving packets between the SGMII interfaces and the cores so you will need to either provide a PASSCLK or select the CORECLK as a source for the PASS PLL. The Gigabit Ethernet switch is a three port switch with two of the ports connected to the external SGMII interfaces and the third connected to the processor subsystem.