I have generated MSI interrupts across the PCIe interface and by calling PCIeTestMsiIrq from within clk0Fxn. Both work but only the first time sending more MSI interrupts across the interface does not result in the interrupt.
7028.PCIe_test1.zip
Mark,
To re-trigger the same interrupt may involve several modules, such as CPU interrupt controller, chip level interrupt controller and PCIe module itself.
I assume you already take care of the interrupt controller for CPU and chip level to clear the flag of that interrupt and it could be re-triggered.
For PCIe itself, we need to clear the status of that MSI vector and write indication to IRQ_EOI register.
For example, if we want to re-trigger MSI_0, after the first time of interrupt, in the ISR, we should
Then we should be able to re-trigger the MSI_0 after exiting the ISR.
Please note that in the current PCIe user guide, there is one typo in MSIx_IRQ_STATUS register that saying writing 0 to clear the status, but it should be writing 1 to clear. This typo will be corrected in the next release.
Please let us know if it is working for you. Thanks.
Sincerely,
Steven
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You metioned I need to 0x4 to the IRQ_EOI register for MSI operation where is this documented and what do I write for the other MSI interrupt groups (1,9,17,25...7,15,23,31))?
I did not see this in the sprug6a document. I did try it however and it worked tahks alot.
Section 1.4.5 in PCIe user guide mentioned that the user software needs to write to EOI register (IRQ_EOI) to notify the end of interrupt.
And in the IRQ_EOI register description, it mentioned that the vector written to the register should be referred in the interrupt event table, which is Table 2-10.
So if you want to use it for other MSI interrupts, you can refer to this table, such as write 5 for (1,9,17,25) and 11 for (7,15,23,31).
Hope it helps.
Yes it does thank you very much. I never made the connection between tis table and the EOI operation.
Hi,
could you please let me see your datasheep.
I am working on Implementing a driver for PCIe but I haven't yet understood how MSI can be implemented
Raya,
The PCIe user guide talks about the MSI interrupt for PCIe and the C6678 data manual has the interrupt event table for all the interrupts.
Basically the MSI should be enabled first in C66x and then the remote device could write to the MSI_IRQ register in the C66x PCIe module to generate the MSI interrupt in the C66x device. The interrupt is connected to the DSP CorePac interrupt controller directly. The interrupt status can be cleared by writing to MSIn_IRQ_STATUS and IRQ_EOI registers.