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TI Home » TI E2E Community » Support Forums » Digital Signal Processors (DSP) » C6000 Multicore DSP » Keystone Multicore Forum (C66, 66A, AM5) » Core connection error
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    Core connection error

    This question is answered
    FeruzM
    Posted by FeruzM
    on Apr 16 2012 03:37 AM
    Intellectual705 points

    Hi everybody,

    I have got error while connecting on my TMSC6678L device

    Connecting Target...
    C66xx_0: GEL Output: DSP core #0
    C66xx_0: GEL Output: No initialization performed since bootmode = 0x00000005
    C66xx_0: GEL Output: You can manually initialize with GlobalDefaultSetup
    
    

    Earlier error was fixed http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/177029.aspx and I am suspecting there is still some sort of configuration error.

    If I try to load program here is what I get

    C66xx_0: File Loader: Data verification failed at address 0x80080000 Please verify target memory and memory map.
    C66xx_0: GEL: File: path/filename.out: a data verification error occurred, file load failed.

    Any help appreciated, thanks!

    Feruz

    target connection globaldefaultsetup
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    • Chad Courtney
      Posted by Chad Courtney
      on Apr 16 2012 08:12 AM
      Mastermind22595 points

      It would appear that you've not configured the DDR memory and you're code has some portion of it located in DDR memory.  When you attempt to load this code to DDR it fails since it's not configured.  You will need to configure the DDR before loading code to it, which can be done via the GEL file.

      Best Regards,

      Chad

      ------------------------------------------------------------------------------------------------------------

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    • FeruzM
      Posted by FeruzM
      on Apr 16 2012 08:31 AM
      Intellectual705 points

      Hi Chad,

      Thank you for respond.

      But I am using given GEL file, in /emulation/boards/evmc6678l/gel/emvc6678l.gel.

      Perhaps, some change in gel file would help?

      Thanks,

      Feruz

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    • Naoki Takahashi
      Posted by Naoki Takahashi
      on Apr 16 2012 09:22 AM
      Prodigy130 points

      Hi FeruzM,

      I do not own the C6678 EVM (I'm a C6670 EVM user), but isn't it related to the DIP SW settings on your EVM?

      I had a quick look at the gel file for C6678 which I found under my CCSv5.1 installation folder.
      The error message seems to come from the following gel codes:

              if (DEVSTAT & 0x0000000E)
              {
                  GEL_TextOut("No initialization performed since bootmode = %x \n",,,,,(DEVSTAT >> 1 ) & 0xF);
                  GEL_TextOut("You can manually initialize with GlobalDefaultSetup\n");
              }else...

      The lower 3 bits of DEVSTAT register tells you the boot device settings, which you can configure by the DIP SW.
      So, how about configuring the EVM for the NO BOOT MODE?

      Oddly, there is no such codes in C6670 EVM's gel...

      BR,
      Naoki

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    • FeruzM
      Posted by FeruzM
      on Apr 16 2012 09:41 AM
      Intellectual705 points

      Hi Naoki,

      Well, I haven't changed anything for long, unless some of my colleagues did, but here: how DIP SW looks

      I hope it is visible!

      btw: using with usb emulator, ccsv5.1

      Thanks!

      Regards,

      Feruz

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    • Chad Courtney
      Posted by Chad Courtney
      on Apr 16 2012 16:30 PM
      Mastermind22595 points

      Feruz,

      Yes, you're loading the GEL file, but if you look at the message, it stops initializing things because you're in I2C boot (bootmode = 5.)  Which is not configuring the DDR memories.  So the DDR memories on not configured and then you try to load the code which some of it is in the DDR memory space, and you get the loading verfication error at 0x80008000.  There's a drop down menu for the GEL and you can go ahead and have the GEL file configure the DDR, which it has not done at this point.  From the GEL menu perform a Global_Default_Setup and this will configure the DDR memory.

      Best Regards,
      Chad

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    • FeruzM
      Posted by FeruzM
      on Apr 25 2012 07:08 AM
      Intellectual705 points

      Hi Chad,

      Thank you for reply. Yes it is working, but how would I do it automatically so that I won't need to make it manually for every core?

      Regards,

      Feruz

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    • Chad Courtney
      Posted by Chad Courtney
      on Apr 25 2012 09:25 AM
      Verified Answer
      Verified by FeruzM
      Mastermind22595 points

      Feruz,

      You would only need to do it once per device, not per core. 

      The DDR needs to be configured before anything is ever written to it.  In a real system where code/data is written to DDR at boot time you can do one of two things.

      1.) Use an intermediate bootloader which configures IPs such as DDR that is required to complete the reset of the bootloading

      2.) Use an IP for bootloading that you can have the host write the config registers for you to do the configuration (SRIO and PCIe are a couple examples of IPs that can do this.)

      That said, for initial development on an EVM people tend not to worry about this as they're focused on the code developement and they just want the DDR to work.  Gel files are general used for this.  I'm assuming CCS is configured to run that GEL script every time you connect to target.  If not I'd suggest you make it do so.  Then go in and modify the GEL script to go ahead and run the initialization routine even though it's done a I2C boot.  In this case every time the DSP goes through a POR or Power Cycle and you have to reconnect w/ CCS, then you'll run the script to initialize DDR automatically.

      Best Regards,

      Chad

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    • FeruzM
      Posted by FeruzM
      on Apr 25 2012 10:09 AM
      Intellectual705 points

      I see!

      Thank you very much!

      Regards,

      Feruz

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