TI E2E Community
Digital Signal Processors (DSP)
C6000 Multicore DSP
Keystone Multicore Forum (C66, 66A, AM5)
How can i perform this two operations in the DSP C6678 of Texas instrument :
- Generating Configuration transactions
- Generating Memory Read from a remote device
i have already configured one DSP C6678 as Root Complex
NB : The example given within the Device treats only memory write
1. In C66x device, the PCIe remote configuration space is located starting from offset 0x2000 (i.e. 0x21802000). The RC could read/write from/to that address space to access the configuration space of remote device and the configuration transactions will be issued automatically. Please note that there is one CFG_SETUP register (offset 0x8) to be configured for different remote devices on the bus. The default values should be working to access the EP directly connected to the RC (without any PCIe switch or bridge).
If there is PCIe switch or bridges in the system, it is better to use certain PCIe host driver on RC side to enumerate the bus and assign the bus/function/device numbers to each device on the PCIe bus.
2. Generating memory read transaction is very similar as generating memory write transaction. The PCIe device could just read from its PCIe data space (i.e. starting from 0x60000000 for C6678 device) using EDMA or CPU read.
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Thank You Steven ,
I understood your answer , but the problem is that the remote device for me is not an other C6678 , it is a bridge function in a switch , so i want to read one register of the bridge
Configuration space and display the value on the console ( screen )
I think the configuration access to bridge or switch from RC should be similar as access to EP.
If the bus/device/function numbers of the Bridge are setup correctly in the RC CFG_SETUP register. The RC could access the configuration registers in the Bridge by reading the remote configuration space (starting from 0x21802000 in C66x PCIe).
Or if there is BAR register in the Bridge which could be mapped to its configuration register space (similar as BAR0 mapping to C66x PCIe apps registers), the RC could generate normal memory write/read to access the Bridge registers with packet address matching to the Bridge BAR register. In this way, the RC should access to the PCIe data space (starting from 0x60000000 in C66x).
Thank you Steven ,
Actualy , i want to access a remote register which is not a PCI Express register , what i want is a function of your module C6678 , which take an adress in parameters and
return the contain of this adress ,
I precise : i have the C6678 as RC , and a bridge in the other side of the link , and i want to acess to a regiser in this bridge , it is sufficient that i use your function : pcie_Readregs(.....,PCIE_LOCATION_REMOTE,...) , while this function can read just a PCIE register
NB: i specified the bus , device , function number of my bridge
If it is not in the PCIe configuration register space in the Bridge, I am afraid you could not use the LLD function directly.
Another way is to do the memory read from the Bridge just as you may intend to do so. You have to configure BAR and other inbound registers in the Bridge to cover the memory location of that register you want to read from Bridge. And configure the RC outbound registers to issue the memory read to the Bridge which is just similar as normal memory read access to the remote device.
Thank you Steven for your answer ,
im trying also to perform a PIPE loopback . How to check that the loopback has been performed correctly if knowing that this kind of loopback doesnt allow looping back
datas and allows just looping back symbols ( mentionned in the document of the C6678 of PCI express module)
PIPE Loopback is a test and debug feature. The Loopback master (such as a PCIe protocol tester) when connected to a device's Link (the device under the test) can place the Link and Loopback slave into the Loopback state by transmitting TS1ordered-sets with the Loopback bit asserted.
If the C66x PCIe module is used as Loopback master, it could put the Loopback slave (at the other end of the PCIe link) into loopback mode by following the programming sequence described in the user guide. And the Loopback slave is better to be a PCIe tester which could decode and display the symbols for the user to monitor the symbols being looping back over the link.
If C66x PCIe module is used as Loopback slave, the Loopback master is better to be a PCIe tester, which could put the Loopback slave into loopback mode and send out the symbols for testing.
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